Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1461138	0	0
cfg0_rd_A	2147483647	3285	0	0
compare_lower0_0_rd_A	2147483647	2977	0	0
compare_upper0_0_rd_A	2147483647	2976	0	0
ctrl_rd_A	2147483647	2934	0	0
intr_enable0_rd_A	2147483647	4065	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1461138	0	0
T11	657118	181069	0	0
T12	0	156372	0	0
T13	0	251481	0	0
T33	0	129	0	0
T37	0	73186	0	0
T38	0	51201	0	0
T39	0	239562	0	0
T40	0	493283	0	0
T41	0	779	0	0
T42	0	666	0	0
T43	445131	0	0	0
T44	235348	0	0	0
T45	199136	0	0	0
T46	328486	0	0	0
T47	488397	0	0	0
T48	2035	0	0	0
T49	10930	0	0	0
T50	153853	0	0	0
T51	454280	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3285	0	0
T11	657118	974	0	0
T31	0	11	0	0
T38	0	649	0	0
T42	0	6	0	0
T43	445131	0	0	0
T44	235348	0	0	0
T45	199136	0	0	0
T46	328486	0	0	0
T47	488397	0	0	0
T48	2035	0	0	0
T49	10930	0	0	0
T50	153853	0	0	0
T51	454280	0	0	0
T52	0	24	0	0
T53	0	6	0	0
T54	0	80	0	0
T55	0	10	0	0
T56	0	40	0	0
T57	0	13	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2977	0	0
T11	657118	1110	0	0
T31	0	5	0	0
T38	0	533	0	0
T42	0	1	0	0
T43	445131	0	0	0
T44	235348	0	0	0
T45	199136	0	0	0
T46	328486	0	0	0
T47	488397	0	0	0
T48	2035	0	0	0
T49	10930	0	0	0
T50	153853	0	0	0
T51	454280	0	0	0
T52	0	13	0	0
T53	0	9	0	0
T54	0	53	0	0
T55	0	10	0	0
T56	0	39	0	0
T57	0	6	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2976	0	0
T11	657118	817	0	0
T31	0	7	0	0
T38	0	596	0	0
T43	445131	0	0	0
T44	235348	0	0	0
T45	199136	0	0	0
T46	328486	0	0	0
T47	488397	0	0	0
T48	2035	0	0	0
T49	10930	0	0	0
T50	153853	0	0	0
T51	454280	0	0	0
T53	0	23	0	0
T54	0	44	0	0
T55	0	5	0	0
T56	0	76	0	0
T58	0	9	0	0
T59	0	11	0	0
T60	0	36	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2934	0	0
T11	657118	1011	0	0
T31	0	6	0	0
T38	0	552	0	0
T42	0	2	0	0
T43	445131	0	0	0
T44	235348	0	0	0
T45	199136	0	0	0
T46	328486	0	0	0
T47	488397	0	0	0
T48	2035	0	0	0
T49	10930	0	0	0
T50	153853	0	0	0
T51	454280	0	0	0
T52	0	10	0	0
T53	0	14	0	0
T54	0	53	0	0
T55	0	14	0	0
T56	0	24	0	0
T57	0	2	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4065	0	0
T11	0	1183	0	0
T34	282881	169	0	0
T35	544133	66	0	0
T36	0	32	0	0
T38	0	486	0	0
T61	0	93	0	0
T62	0	34	0	0
T63	0	33	0	0
T64	0	37	0	0
T65	0	42	0	0
T66	274433	0	0	0
T67	394193	0	0	0
T68	541213	0	0	0
T69	134387	0	0	0
T70	403868	0	0	0
T71	369469	0	0	0
T72	257964	0	0	0
T73	413728	0	0	0