Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53152391	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	54657768	1		T1	291926		T2	1297		T3	395229

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	106513808	1		T1	583673		T2	2545		T3	788718
values[0x0]	616295	1		T1	119		T2	9		T3	18
values[0x1]	680056	1		T1	103		T2	11		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42436047	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	65374112	1		T1	350643		T2	1584		T3	474650

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	623259	1		T2	10		T3	3034		T4	2519
valid_sources[0x01]	310100	1		T2	8		T3	3179		T4	2581
valid_sources[0x02]	323632	1		T2	14		T3	2999		T4	2510
valid_sources[0x03]	388256	1		T2	29		T3	3171		T4	2580
valid_sources[0x04]	309729	1		T2	5		T3	2997		T4	2634
valid_sources[0x05]	385940	1		T3	3087		T4	2470		T6	72770
valid_sources[0x06]	315511	1		T2	4		T3	3137		T4	2700
valid_sources[0x07]	310474	1		T2	5		T3	3184		T4	2593
valid_sources[0x08]	314422	1		T2	8		T3	3037		T4	2547
valid_sources[0x09]	311575	1		T3	3104		T4	2603		T8	1561
valid_sources[0x0a]	312488	1		T2	4		T3	3076		T4	2611
valid_sources[0x0b]	312956	1		T2	6		T3	3104		T4	2571
valid_sources[0x0c]	323429	1		T2	9		T3	3204		T4	2591
valid_sources[0x0d]	314446	1		T2	3		T3	3057		T4	2670
valid_sources[0x0e]	318756	1		T2	1		T3	3107		T4	2590
valid_sources[0x0f]	537023	1		T2	8		T3	3251		T4	2559
valid_sources[0x10]	310126	1		T2	6		T3	3090		T4	2499
valid_sources[0x11]	314027	1		T2	11		T3	3071		T4	2349
valid_sources[0x12]	314542	1		T2	11		T3	3090		T4	2684
valid_sources[0x13]	312841	1		T2	15		T3	3149		T4	2455
valid_sources[0x14]	310929	1		T2	5		T3	3074		T4	2573
valid_sources[0x15]	309030	1		T2	17		T3	3131		T4	2518
valid_sources[0x16]	313966	1		T2	6		T3	3100		T4	2410
valid_sources[0x17]	311443	1		T2	10		T3	3089		T4	2641
valid_sources[0x18]	311788	1		T2	9		T3	3112		T4	2686
valid_sources[0x19]	309048	1		T2	14		T3	3168		T4	2507
valid_sources[0x1a]	314700	1		T2	5		T3	3026		T4	2561
valid_sources[0x1b]	311760	1		T2	8		T3	3077		T4	2753
valid_sources[0x1c]	312625	1		T2	1		T3	3009		T4	2591
valid_sources[0x1d]	311148	1		T2	12		T3	3112		T4	2574
valid_sources[0x1e]	310128	1		T2	2		T3	2975		T4	2463
valid_sources[0x1f]	360311	1		T2	17		T3	3133		T4	2542
valid_sources[0x20]	305889	1		T2	11		T3	3124		T4	2568
valid_sources[0x21]	514279	1		T2	8		T3	3095		T4	2463
valid_sources[0x22]	346983	1		T2	19		T3	3048		T4	2508
valid_sources[0x23]	311241	1		T2	17		T3	3157		T4	2534
valid_sources[0x24]	311678	1		T2	12		T3	3021		T4	2515
valid_sources[0x25]	312329	1		T2	9		T3	3191		T4	2565
valid_sources[0x26]	309992	1		T2	11		T3	3071		T4	2637
valid_sources[0x27]	324696	1		T2	19		T3	3012		T4	2452
valid_sources[0x28]	313872	1		T2	7		T3	3213		T4	2506
valid_sources[0x29]	311044	1		T2	8		T3	3070		T4	2615
valid_sources[0x2a]	311934	1		T2	5		T3	2906		T4	2734
valid_sources[0x2b]	313115	1		T2	13		T3	3106		T4	2584
valid_sources[0x2c]	309117	1		T2	32		T3	3061		T4	2485
valid_sources[0x2d]	318691	1		T2	5		T3	3065		T4	2502
valid_sources[0x2e]	309596	1		T2	4		T3	3012		T4	2666
valid_sources[0x2f]	311462	1		T2	10		T3	3061		T4	2609
valid_sources[0x30]	1065278	1		T2	20		T3	3126		T4	2613
valid_sources[0x31]	566005	1		T2	3		T3	3116		T4	2533
valid_sources[0x32]	312011	1		T2	13		T3	2922		T4	2470
valid_sources[0x33]	777233	1		T2	7		T3	2983		T4	2622
valid_sources[0x34]	385242	1		T2	3		T3	3258		T4	2648
valid_sources[0x35]	311894	1		T2	1		T3	3057		T4	2572
valid_sources[0x36]	312455	1		T2	10		T3	3088		T4	2694
valid_sources[0x37]	634126	1		T2	6		T3	3019		T4	2568
valid_sources[0x38]	311858	1		T2	14		T3	3198		T4	2613
valid_sources[0x39]	658860	1		T2	14		T3	3047		T4	2672
valid_sources[0x3a]	314479	1		T3	3083		T4	2648		T8	1607
valid_sources[0x3b]	319664	1		T2	5		T3	3088		T4	2567
valid_sources[0x3c]	310113	1		T2	10		T3	3084		T4	2480
valid_sources[0x3d]	312531	1		T2	6		T3	3114		T4	2620
valid_sources[0x3e]	313571	1		T2	18		T3	3186		T4	2642
valid_sources[0x3f]	2228447	1		T2	6		T3	3102		T4	2506
valid_sources[0x40]	339202	1		T2	4		T3	3159		T4	2547
valid_sources[0x41]	309901	1		T2	13		T3	3060		T4	2524
valid_sources[0x42]	310865	1		T2	12		T3	3159		T4	2615
valid_sources[0x43]	345983	1		T2	20		T3	3038		T4	2607
valid_sources[0x44]	312749	1		T2	16		T3	3168		T4	2610
valid_sources[0x45]	310111	1		T2	21		T3	3154		T4	2488
valid_sources[0x46]	312462	1		T2	11		T3	3021		T4	2522
valid_sources[0x47]	310786	1		T2	19		T3	3148		T4	2481
valid_sources[0x48]	905275	1		T2	8		T3	3068		T4	2612
valid_sources[0x49]	306967	1		T2	4		T3	2994		T4	2647
valid_sources[0x4a]	310850	1		T2	7		T3	3085		T4	2363
valid_sources[0x4b]	312059	1		T2	8		T3	3033		T4	2492
valid_sources[0x4c]	313035	1		T2	8		T3	3024		T4	2558
valid_sources[0x4d]	310242	1		T2	9		T3	3155		T4	2573
valid_sources[0x4e]	310137	1		T2	12		T3	3040		T4	2573
valid_sources[0x4f]	598705	1		T2	11		T3	3048		T4	2765
valid_sources[0x50]	310446	1		T2	17		T3	3101		T4	2583
valid_sources[0x51]	308578	1		T2	11		T3	3000		T4	2672
valid_sources[0x52]	314091	1		T2	15		T3	2984		T4	2603
valid_sources[0x53]	583559	1		T2	7		T3	3335		T4	2543
valid_sources[0x54]	310067	1		T2	7		T3	3017		T4	2429
valid_sources[0x55]	312173	1		T2	14		T3	3081		T4	2629
valid_sources[0x56]	1081448	1		T2	16		T3	3017		T4	2723
valid_sources[0x57]	313278	1		T2	10		T3	3133		T4	2596
valid_sources[0x58]	311797	1		T2	11		T3	3108		T4	2614
valid_sources[0x59]	312975	1		T2	14		T3	3028		T4	2643
valid_sources[0x5a]	308693	1		T2	12		T3	3105		T4	2471
valid_sources[0x5b]	309652	1		T2	8		T3	2980		T4	2611
valid_sources[0x5c]	967500	1		T2	12		T3	3099		T4	2524
valid_sources[0x5d]	310426	1		T2	11		T3	3199		T4	2649
valid_sources[0x5e]	307395	1		T2	11		T3	3124		T4	2643
valid_sources[0x5f]	314559	1		T2	7		T3	3166		T4	2518
valid_sources[0x60]	820028	1		T2	17		T3	3273		T4	2545
valid_sources[0x61]	311734	1		T2	21		T3	3080		T4	2602
valid_sources[0x62]	1057018	1		T2	16		T3	3243		T4	2506
valid_sources[0x63]	310194	1		T2	7		T3	3108		T4	2509
valid_sources[0x64]	313318	1		T2	8		T3	3081		T4	2568
valid_sources[0x65]	309567	1		T2	13		T3	3114		T4	2511
valid_sources[0x66]	309371	1		T2	18		T3	3100		T4	2521
valid_sources[0x67]	309962	1		T2	11		T3	3062		T4	2635
valid_sources[0x68]	310509	1		T2	14		T3	3101		T4	2611
valid_sources[0x69]	313286	1		T2	2		T3	3013		T4	2632
valid_sources[0x6a]	313010	1		T2	8		T3	3134		T4	2634
valid_sources[0x6b]	324351	1		T2	9		T3	3016		T4	2382
valid_sources[0x6c]	310986	1		T2	3		T3	3026		T4	2562
valid_sources[0x6d]	751910	1		T2	3		T3	3039		T4	2610
valid_sources[0x6e]	314927	1		T2	4		T3	3227		T4	2638
valid_sources[0x6f]	315737	1		T2	10		T3	3078		T4	2433
valid_sources[0x70]	310726	1		T2	11		T3	3156		T4	2515
valid_sources[0x71]	314272	1		T2	11		T3	3091		T4	2479
valid_sources[0x72]	313431	1		T2	5		T3	3025		T4	2616
valid_sources[0x73]	507754	1		T2	12		T3	3074		T4	2590
valid_sources[0x74]	435159	1		T2	5		T3	3154		T4	2563
valid_sources[0x75]	312865	1		T2	7		T3	3067		T4	2548
valid_sources[0x76]	1161853	1		T2	6		T3	3051		T4	2610
valid_sources[0x77]	715550	1		T2	4		T3	3144		T4	2543
valid_sources[0x78]	311945	1		T2	5		T3	3110		T4	2566
valid_sources[0x79]	311695	1		T2	12		T3	3123		T4	2521
valid_sources[0x7a]	429725	1		T2	11		T3	3105		T4	2633
valid_sources[0x7b]	310366	1		T2	8		T3	3012		T4	2657
valid_sources[0x7c]	311621	1		T2	11		T3	3060		T4	2553
valid_sources[0x7d]	313839	1		T2	16		T3	3176		T4	2590
valid_sources[0x7e]	309276	1		T2	6		T3	3151		T4	2603
valid_sources[0x7f]	311429	1		T2	8		T3	3177		T4	2519
valid_sources[0x80]	312165	1		T2	13		T3	3028		T4	2614

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53450004

1

T1

291772

T2

1280

T3

395202

values[0x0]

all_enables

biggest_size

604701

1

T1

88

T2

8

T3

12

values[0x1]

all_enables

biggest_size

603063

1

T1

66

T2

9

T3

15