Module Definition
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Module : rv_timer_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_timer_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_timer_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.83 100.00 83.33 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_timer_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 2147483647 2100895 0 0
cfg0_rd_A 2147483647 4393 0 0
compare_lower0_0_rd_A 2147483647 4225 0 0
compare_upper0_0_rd_A 2147483647 4192 0 0
ctrl_rd_A 2147483647 4117 0 0
intr_enable0_rd_A 2147483647 5254 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2100895 0 0
T13 308784 86177 0 0
T14 272620 113129 0 0
T15 0 108941 0 0
T16 3595 0 0 0
T21 335848 0 0 0
T22 262847 0 0 0
T23 865299 0 0 0
T24 483505 0 0 0
T36 0 266667 0 0
T37 0 78275 0 0
T38 0 141025 0 0
T39 0 303443 0 0
T40 0 281588 0 0
T41 0 223186 0 0
T42 0 145090 0 0
T43 775416 0 0 0
T44 665838 0 0 0
T45 494934 0 0 0

cfg0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 4393 0 0
T13 308784 538 0 0
T14 272620 0 0 0
T15 0 1006 0 0
T16 3595 0 0 0
T21 335848 0 0 0
T22 262847 0 0 0
T23 865299 0 0 0
T24 483505 0 0 0
T33 0 5 0 0
T37 0 744 0 0
T43 775416 0 0 0
T44 665838 0 0 0
T45 494934 0 0 0
T46 0 504 0 0
T47 0 20 0 0
T48 0 5 0 0
T49 0 12 0 0
T50 0 158 0 0
T51 0 11 0 0

compare_lower0_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 4225 0 0
T13 308784 515 0 0
T14 272620 0 0 0
T15 0 1107 0 0
T16 3595 0 0 0
T21 335848 0 0 0
T22 262847 0 0 0
T23 865299 0 0 0
T24 483505 0 0 0
T33 0 5 0 0
T37 0 914 0 0
T43 775416 0 0 0
T44 665838 0 0 0
T45 494934 0 0 0
T46 0 457 0 0
T47 0 3 0 0
T48 0 18 0 0
T49 0 17 0 0
T50 0 94 0 0
T51 0 7 0 0

compare_upper0_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 4192 0 0
T13 308784 455 0 0
T14 272620 0 0 0
T15 0 1248 0 0
T16 3595 0 0 0
T21 335848 0 0 0
T22 262847 0 0 0
T23 865299 0 0 0
T24 483505 0 0 0
T33 0 8 0 0
T37 0 736 0 0
T43 775416 0 0 0
T44 665838 0 0 0
T45 494934 0 0 0
T46 0 504 0 0
T47 0 9 0 0
T48 0 13 0 0
T49 0 8 0 0
T50 0 137 0 0
T51 0 9 0 0

ctrl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 4117 0 0
T13 308784 463 0 0
T14 272620 0 0 0
T15 0 1104 0 0
T16 3595 0 0 0
T21 335848 0 0 0
T22 262847 0 0 0
T23 865299 0 0 0
T24 483505 0 0 0
T33 0 7 0 0
T37 0 757 0 0
T43 775416 0 0 0
T44 665838 0 0 0
T45 494934 0 0 0
T46 0 564 0 0
T47 0 16 0 0
T48 0 5 0 0
T49 0 14 0 0
T50 0 121 0 0
T52 0 3 0 0

intr_enable0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 5254 0 0
T13 308784 585 0 0
T14 272620 0 0 0
T15 0 1270 0 0
T16 3595 0 0 0
T21 335848 0 0 0
T22 262847 0 0 0
T23 865299 0 0 0
T24 483505 0 0 0
T37 0 955 0 0
T43 775416 0 0 0
T44 665838 0 0 0
T45 494934 0 0 0
T46 0 663 0 0
T53 0 43 0 0
T54 0 31 0 0
T55 0 38 0 0
T56 0 80 0 0
T57 0 84 0 0
T58 0 44 0 0

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