Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58498314	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	60090428	1		T1	90223		T2	5630		T3	688

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	117218131	1		T1	180085		T2	11072		T3	1368
values[0x0]	650254	1		T1	35		T2	6		T3	21
values[0x1]	720357	1		T1	27		T2	15		T3	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46707413	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	71881329	1		T1	108227		T2	6740		T3	844

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	328621	1		T1	679		T2	47		T3	11
valid_sources[0x01]	331059	1		T1	689		T2	35		T4	2190
valid_sources[0x02]	349844	1		T1	734		T2	43		T3	5
valid_sources[0x03]	329893	1		T1	773		T2	52		T3	5
valid_sources[0x04]	344926	1		T1	678		T2	40		T3	6
valid_sources[0x05]	326117	1		T1	735		T2	38		T3	9
valid_sources[0x06]	326845	1		T1	663		T2	37		T3	6
valid_sources[0x07]	331024	1		T1	799		T2	57		T3	4
valid_sources[0x08]	327057	1		T1	677		T2	51		T3	4
valid_sources[0x09]	330065	1		T1	619		T2	50		T4	2293
valid_sources[0x0a]	327610	1		T1	715		T2	45		T4	2251
valid_sources[0x0b]	328819	1		T1	695		T2	35		T3	3
valid_sources[0x0c]	328056	1		T1	751		T2	37		T3	14
valid_sources[0x0d]	326301	1		T1	750		T2	44		T3	4
valid_sources[0x0e]	329723	1		T1	631		T2	35		T3	9
valid_sources[0x0f]	330953	1		T1	638		T2	41		T3	3
valid_sources[0x10]	327473	1		T1	708		T2	45		T3	3
valid_sources[0x11]	355930	1		T1	698		T2	41		T3	1
valid_sources[0x12]	328989	1		T1	731		T2	50		T3	10
valid_sources[0x13]	326677	1		T1	675		T2	33		T3	3
valid_sources[0x14]	325846	1		T1	666		T2	47		T3	1
valid_sources[0x15]	328329	1		T1	707		T2	43		T3	2
valid_sources[0x16]	328041	1		T1	697		T2	44		T3	8
valid_sources[0x17]	331935	1		T1	655		T2	46		T4	2300
valid_sources[0x18]	478577	1		T1	760		T2	38		T3	3
valid_sources[0x19]	330389	1		T1	721		T2	46		T3	3
valid_sources[0x1a]	327128	1		T1	680		T2	47		T3	2
valid_sources[0x1b]	327030	1		T1	708		T2	36		T3	20
valid_sources[0x1c]	329104	1		T1	732		T2	47		T3	6
valid_sources[0x1d]	447673	1		T1	737		T2	49		T3	9
valid_sources[0x1e]	376098	1		T1	708		T2	44		T3	11
valid_sources[0x1f]	327418	1		T1	651		T2	39		T3	7
valid_sources[0x20]	325825	1		T1	674		T2	36		T3	13
valid_sources[0x21]	329734	1		T1	733		T2	46		T3	1
valid_sources[0x22]	328031	1		T1	685		T2	34		T3	6
valid_sources[0x23]	1114385	1		T1	721		T2	53		T3	4
valid_sources[0x24]	328376	1		T1	710		T2	43		T3	5
valid_sources[0x25]	328733	1		T1	695		T2	50		T3	17
valid_sources[0x26]	328542	1		T1	690		T2	39		T3	7
valid_sources[0x27]	328235	1		T1	656		T2	45		T3	1
valid_sources[0x28]	329600	1		T1	674		T2	48		T3	3
valid_sources[0x29]	328068	1		T1	681		T2	34		T3	5
valid_sources[0x2a]	327278	1		T1	718		T2	32		T3	7
valid_sources[0x2b]	327866	1		T1	648		T2	46		T3	16
valid_sources[0x2c]	329321	1		T1	759		T2	54		T3	1
valid_sources[0x2d]	331313	1		T1	728		T2	50		T3	7
valid_sources[0x2e]	327132	1		T1	712		T2	38		T3	7
valid_sources[0x2f]	404474	1		T1	662		T2	48		T3	4
valid_sources[0x30]	328573	1		T1	681		T2	48		T3	5
valid_sources[0x31]	326984	1		T1	684		T2	38		T3	5
valid_sources[0x32]	341334	1		T1	776		T2	43		T3	9
valid_sources[0x33]	328807	1		T1	717		T2	42		T3	9
valid_sources[0x34]	326957	1		T1	686		T2	54		T3	3
valid_sources[0x35]	327892	1		T1	653		T2	47		T3	9
valid_sources[0x36]	326751	1		T1	667		T2	56		T3	5
valid_sources[0x37]	328599	1		T1	733		T2	42		T3	3
valid_sources[0x38]	364614	1		T1	676		T2	52		T3	12
valid_sources[0x39]	327121	1		T1	650		T2	47		T3	10
valid_sources[0x3a]	336523	1		T1	647		T2	40		T3	3
valid_sources[0x3b]	339143	1		T1	645		T2	44		T3	6
valid_sources[0x3c]	359202	1		T1	707		T2	51		T3	14
valid_sources[0x3d]	411681	1		T1	662		T2	49		T3	6
valid_sources[0x3e]	327170	1		T1	702		T2	52		T3	6
valid_sources[0x3f]	327284	1		T1	732		T2	50		T3	1
valid_sources[0x40]	328185	1		T1	722		T2	48		T3	8
valid_sources[0x41]	2041789	1		T1	656		T2	47		T3	6
valid_sources[0x42]	328536	1		T1	681		T2	30		T3	4
valid_sources[0x43]	329185	1		T1	744		T2	51		T3	9
valid_sources[0x44]	329660	1		T1	725		T2	36		T3	8
valid_sources[0x45]	330089	1		T1	704		T2	46		T3	9
valid_sources[0x46]	329043	1		T1	714		T2	36		T3	5
valid_sources[0x47]	563729	1		T1	726		T2	42		T3	12
valid_sources[0x48]	328551	1		T1	705		T2	40		T4	2361
valid_sources[0x49]	333565	1		T1	715		T2	59		T3	2
valid_sources[0x4a]	373601	1		T1	713		T2	37		T3	3
valid_sources[0x4b]	328410	1		T1	708		T2	39		T3	2
valid_sources[0x4c]	328193	1		T1	659		T2	57		T3	9
valid_sources[0x4d]	329167	1		T1	710		T2	43		T3	10
valid_sources[0x4e]	328444	1		T1	689		T2	42		T3	6
valid_sources[0x4f]	770767	1		T1	727		T2	36		T4	2210
valid_sources[0x50]	328386	1		T1	685		T2	40		T3	6
valid_sources[0x51]	331041	1		T1	672		T2	35		T3	1
valid_sources[0x52]	329355	1		T1	643		T2	43		T3	10
valid_sources[0x53]	427974	1		T1	706		T2	48		T3	14
valid_sources[0x54]	327289	1		T1	673		T2	43		T4	2300
valid_sources[0x55]	464115	1		T1	684		T2	38		T3	5
valid_sources[0x56]	327757	1		T1	696		T2	56		T3	1
valid_sources[0x57]	329495	1		T1	718		T2	48		T4	2349
valid_sources[0x58]	328120	1		T1	685		T2	31		T3	3
valid_sources[0x59]	541860	1		T1	667		T2	33		T3	16
valid_sources[0x5a]	552008	1		T1	690		T2	46		T3	2
valid_sources[0x5b]	329262	1		T1	771		T2	49		T3	6
valid_sources[0x5c]	326971	1		T1	704		T2	33		T3	6
valid_sources[0x5d]	327191	1		T1	728		T2	52		T3	3
valid_sources[0x5e]	367063	1		T1	688		T2	52		T3	10
valid_sources[0x5f]	746143	1		T1	636		T2	59		T3	7
valid_sources[0x60]	328735	1		T1	738		T2	37		T3	8
valid_sources[0x61]	327087	1		T1	729		T2	45		T3	10
valid_sources[0x62]	329700	1		T1	748		T2	37		T3	17
valid_sources[0x63]	407274	1		T1	720		T2	45		T3	10
valid_sources[0x64]	329569	1		T1	704		T2	42		T3	7
valid_sources[0x65]	328264	1		T1	706		T2	55		T3	19
valid_sources[0x66]	501779	1		T1	704		T2	48		T3	3
valid_sources[0x67]	833582	1		T1	719		T2	45		T3	2
valid_sources[0x68]	327020	1		T1	635		T2	44		T3	5
valid_sources[0x69]	330458	1		T1	704		T2	52		T3	2
valid_sources[0x6a]	5712265	1		T1	754		T2	29		T3	4
valid_sources[0x6b]	326969	1		T1	799		T2	45		T3	14
valid_sources[0x6c]	604908	1		T1	685		T2	51		T3	2
valid_sources[0x6d]	325042	1		T1	694		T2	35		T3	14
valid_sources[0x6e]	328218	1		T1	752		T2	35		T3	9
valid_sources[0x6f]	328379	1		T1	707		T2	59		T3	4
valid_sources[0x70]	332706	1		T1	698		T2	42		T3	3
valid_sources[0x71]	327708	1		T1	760		T2	35		T3	5
valid_sources[0x72]	341860	1		T1	822		T2	47		T3	7
valid_sources[0x73]	328183	1		T1	666		T2	28		T3	7
valid_sources[0x74]	536838	1		T1	675		T2	44		T3	3
valid_sources[0x75]	326783	1		T1	734		T2	47		T3	14
valid_sources[0x76]	327100	1		T1	651		T2	45		T3	6
valid_sources[0x77]	327060	1		T1	727		T2	34		T3	14
valid_sources[0x78]	692235	1		T1	612		T2	29		T3	1
valid_sources[0x79]	341918	1		T1	674		T2	58		T4	2264
valid_sources[0x7a]	327975	1		T1	691		T2	47		T3	5
valid_sources[0x7b]	326027	1		T1	727		T2	55		T3	3
valid_sources[0x7c]	325939	1		T1	738		T2	39		T3	4
valid_sources[0x7d]	370752	1		T1	711		T2	47		T3	11
valid_sources[0x7e]	336865	1		T1	630		T2	35		T3	5
valid_sources[0x7f]	331219	1		T1	706		T2	53		T3	1
valid_sources[0x80]	328253	1		T1	614		T2	38		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

58812543

1

T1

90172

T2

5617

T3

659

values[0x0]

all_enables

biggest_size

638358

1

T1

30

T2

5

T3

17

values[0x1]

all_enables

biggest_size

639527

1

T1

21

T2

8

T3

12