Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2216002	0	0
cfg0_rd_A	2147483647	6653	0	0
compare_lower0_0_rd_A	2147483647	6672	0	0
compare_upper0_0_rd_A	2147483647	6343	0	0
ctrl_rd_A	2147483647	6026	0	0
intr_enable0_rd_A	2147483647	7690	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2216002	0	0
T5	283661	78287	0	0
T6	216989	0	0	0
T7	835993	0	0	0
T8	175729	0	0	0
T9	969336	0	0	0
T10	885416	0	0	0
T11	0	471299	0	0
T12	0	170881	0	0
T31	0	104923	0	0
T32	0	168074	0	0
T33	0	72778	0	0
T34	0	48271	0	0
T35	0	68480	0	0
T36	0	214011	0	0
T37	0	167042	0	0
T38	113163	0	0	0
T39	911826	0	0	0
T40	107210	0	0	0
T41	339127	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6653	0	0
T29	0	69	0	0
T30	0	61	0	0
T36	823363	2182	0	0
T37	660147	1632	0	0
T42	0	311	0	0
T43	0	672	0	0
T44	0	65	0	0
T45	0	5	0	0
T46	0	1	0	0
T47	0	43	0	0
T48	143296	0	0	0
T49	100010	0	0	0
T50	142208	0	0	0
T51	593793	0	0	0
T52	336212	0	0	0
T53	114406	0	0	0
T54	174313	0	0	0
T55	559650	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6672	0	0
T29	0	34	0	0
T30	0	52	0	0
T36	823363	2329	0	0
T37	660147	1787	0	0
T42	0	310	0	0
T43	0	613	0	0
T44	0	60	0	0
T45	0	8	0	0
T46	0	8	0	0
T47	0	30	0	0
T48	143296	0	0	0
T49	100010	0	0	0
T50	142208	0	0	0
T51	593793	0	0	0
T52	336212	0	0	0
T53	114406	0	0	0
T54	174313	0	0	0
T55	559650	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6343	0	0
T29	0	40	0	0
T30	0	54	0	0
T36	823363	2134	0	0
T37	660147	1680	0	0
T42	0	237	0	0
T43	0	632	0	0
T44	0	36	0	0
T45	0	8	0	0
T46	0	15	0	0
T47	0	35	0	0
T48	143296	0	0	0
T49	100010	0	0	0
T50	142208	0	0	0
T51	593793	0	0	0
T52	336212	0	0	0
T53	114406	0	0	0
T54	174313	0	0	0
T55	559650	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6026	0	0
T29	0	25	0	0
T30	0	31	0	0
T36	823363	1998	0	0
T37	660147	1727	0	0
T42	0	253	0	0
T43	0	597	0	0
T44	0	40	0	0
T45	0	3	0	0
T46	0	10	0	0
T47	0	13	0	0
T48	143296	0	0	0
T49	100010	0	0	0
T50	142208	0	0	0
T51	593793	0	0	0
T52	336212	0	0	0
T53	114406	0	0	0
T54	174313	0	0	0
T55	559650	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7690	0	0
T36	0	2500	0	0
T37	0	1978	0	0
T42	0	353	0	0
T56	354059	47	0	0
T57	170886	24	0	0
T58	0	37	0	0
T59	0	111	0	0
T60	0	32	0	0
T61	0	70	0	0
T62	0	31	0	0
T63	773820	0	0	0
T64	778889	0	0	0
T65	952431	0	0	0
T66	174319	0	0	0
T67	129187	0	0	0
T68	116781	0	0	0
T69	841497	0	0	0
T70	142858	0	0	0