Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67056500	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	68557459	1		T1	3007		T2	129421		T3	9543

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	134315488	1		T1	5959		T2	258132		T3	19034
values[0x0]	618225	1		T1	22		T2	7		T3	21
values[0x1]	680246	1		T1	12		T2	3		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53553226	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	82060733	1		T1	3592		T2	155368		T3	11493

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	993611	1		T1	18		T2	882		T3	52
valid_sources[0x01]	399295	1		T1	38		T2	1000		T3	93
valid_sources[0x02]	402711	1		T1	31		T2	962		T3	45
valid_sources[0x03]	401784	1		T1	71		T2	971		T3	113
valid_sources[0x04]	400340	1		T1	16		T2	851		T3	73
valid_sources[0x05]	402616	1		T1	14		T2	1033		T3	62
valid_sources[0x06]	400473	1		T1	37		T2	1059		T3	73
valid_sources[0x07]	398480	1		T1	40		T2	1023		T3	96
valid_sources[0x08]	401454	1		T1	56		T2	1060		T3	98
valid_sources[0x09]	400459	1		T1	24		T2	845		T3	68
valid_sources[0x0a]	439043	1		T2	1094		T3	54		T4	1526
valid_sources[0x0b]	404175	1		T1	26		T2	1005		T3	81
valid_sources[0x0c]	492570	1		T1	27		T2	1067		T3	89
valid_sources[0x0d]	834091	1		T1	5		T2	1008		T3	99
valid_sources[0x0e]	398008	1		T1	42		T2	1004		T3	85
valid_sources[0x0f]	397908	1		T1	15		T2	975		T3	68
valid_sources[0x10]	398582	1		T1	30		T2	1036		T3	68
valid_sources[0x11]	401601	1		T1	32		T2	956		T3	82
valid_sources[0x12]	401051	1		T1	6		T2	1087		T3	104
valid_sources[0x13]	400592	1		T1	38		T2	1030		T3	89
valid_sources[0x14]	400198	1		T1	28		T2	869		T3	51
valid_sources[0x15]	400602	1		T1	4		T2	964		T3	82
valid_sources[0x16]	459431	1		T2	957		T3	83		T4	1460
valid_sources[0x17]	841189	1		T1	12		T2	986		T3	56
valid_sources[0x18]	401029	1		T1	29		T2	1016		T3	66
valid_sources[0x19]	402477	1		T1	15		T2	967		T3	89
valid_sources[0x1a]	398743	1		T1	2		T2	1041		T3	101
valid_sources[0x1b]	403723	1		T1	24		T2	946		T3	99
valid_sources[0x1c]	400242	1		T1	13		T2	1119		T3	95
valid_sources[0x1d]	414250	1		T1	6		T2	969		T3	92
valid_sources[0x1e]	399938	1		T1	10		T2	1019		T3	70
valid_sources[0x1f]	399169	1		T1	11		T2	1014		T3	83
valid_sources[0x20]	400875	1		T1	21		T2	979		T3	53
valid_sources[0x21]	402552	1		T1	31		T2	1109		T3	60
valid_sources[0x22]	1929674	1		T1	7		T2	1154		T3	95
valid_sources[0x23]	1116312	1		T1	31		T2	932		T3	53
valid_sources[0x24]	1419401	1		T1	45		T2	989		T3	73
valid_sources[0x25]	408908	1		T1	12		T2	963		T3	79
valid_sources[0x26]	397475	1		T1	10		T2	1004		T3	65
valid_sources[0x27]	396885	1		T1	44		T2	971		T3	111
valid_sources[0x28]	403622	1		T1	53		T2	979		T3	58
valid_sources[0x29]	401095	1		T1	40		T2	895		T3	32
valid_sources[0x2a]	425546	1		T1	9		T2	1008		T3	58
valid_sources[0x2b]	399889	1		T1	18		T2	867		T3	61
valid_sources[0x2c]	412107	1		T1	27		T2	981		T3	102
valid_sources[0x2d]	399660	1		T1	34		T2	1094		T3	82
valid_sources[0x2e]	399470	1		T1	27		T2	1183		T3	70
valid_sources[0x2f]	399766	1		T1	12		T2	898		T3	50
valid_sources[0x30]	397158	1		T1	15		T2	895		T3	87
valid_sources[0x31]	401890	1		T1	40		T2	1114		T3	23
valid_sources[0x32]	403663	1		T1	34		T2	1108		T3	59
valid_sources[0x33]	517036	1		T1	16		T2	936		T3	62
valid_sources[0x34]	402380	1		T1	29		T2	1064		T3	72
valid_sources[0x35]	400048	1		T1	19		T2	1020		T3	40
valid_sources[0x36]	400822	1		T1	49		T2	1033		T3	86
valid_sources[0x37]	417616	1		T1	35		T2	944		T3	54
valid_sources[0x38]	403700	1		T1	24		T2	991		T3	56
valid_sources[0x39]	400703	1		T1	30		T2	989		T3	57
valid_sources[0x3a]	400204	1		T1	14		T2	1003		T3	67
valid_sources[0x3b]	401565	1		T1	37		T2	951		T3	68
valid_sources[0x3c]	398392	1		T1	30		T2	1064		T3	35
valid_sources[0x3d]	2572466	1		T1	25		T2	899		T3	42
valid_sources[0x3e]	400089	1		T1	25		T2	1016		T3	74
valid_sources[0x3f]	1843161	1		T1	14		T2	990		T3	110
valid_sources[0x40]	395499	1		T1	33		T2	1155		T3	103
valid_sources[0x41]	401226	1		T1	8		T2	1001		T3	74
valid_sources[0x42]	473195	1		T1	3		T2	1086		T3	80
valid_sources[0x43]	2998673	1		T1	15		T2	1003		T3	32
valid_sources[0x44]	404596	1		T1	20		T2	969		T3	79
valid_sources[0x45]	401708	1		T1	89		T2	1056		T3	60
valid_sources[0x46]	398262	1		T1	11		T2	1052		T3	87
valid_sources[0x47]	401779	1		T1	26		T2	881		T3	62
valid_sources[0x48]	399302	1		T1	9		T2	1102		T3	48
valid_sources[0x49]	426183	1		T1	10		T2	1109		T3	60
valid_sources[0x4a]	402228	1		T1	18		T2	967		T3	77
valid_sources[0x4b]	406315	1		T1	18		T2	963		T3	45
valid_sources[0x4c]	413168	1		T1	26		T2	1101		T3	63
valid_sources[0x4d]	401348	1		T1	12		T2	1108		T3	99
valid_sources[0x4e]	402897	1		T1	8		T2	1012		T3	69
valid_sources[0x4f]	401335	1		T1	6		T2	1018		T3	60
valid_sources[0x50]	398875	1		T1	21		T2	988		T3	79
valid_sources[0x51]	402841	1		T1	79		T2	948		T3	49
valid_sources[0x52]	909882	1		T1	1		T2	932		T3	95
valid_sources[0x53]	397061	1		T1	22		T2	1036		T3	23
valid_sources[0x54]	397870	1		T1	18		T2	1242		T3	98
valid_sources[0x55]	422346	1		T2	990		T3	46		T4	1443
valid_sources[0x56]	396563	1		T1	9		T2	1066		T3	82
valid_sources[0x57]	403747	1		T1	21		T2	1031		T3	81
valid_sources[0x58]	399143	1		T1	22		T2	1021		T3	102
valid_sources[0x59]	400203	1		T1	7		T2	980		T3	62
valid_sources[0x5a]	503007	1		T1	51		T2	993		T3	84
valid_sources[0x5b]	399028	1		T1	39		T2	1067		T3	97
valid_sources[0x5c]	402474	1		T1	23		T2	1123		T3	68
valid_sources[0x5d]	402527	1		T1	4		T2	1002		T3	117
valid_sources[0x5e]	400413	1		T1	7		T2	950		T3	88
valid_sources[0x5f]	402259	1		T1	29		T2	1078		T3	53
valid_sources[0x60]	399543	1		T1	21		T2	894		T3	110
valid_sources[0x61]	403027	1		T1	15		T2	958		T3	84
valid_sources[0x62]	400286	1		T1	48		T2	1177		T3	64
valid_sources[0x63]	564328	1		T1	28		T2	1125		T3	75
valid_sources[0x64]	421319	1		T1	21		T2	1100		T3	94
valid_sources[0x65]	397372	1		T1	35		T2	946		T3	67
valid_sources[0x66]	401307	1		T1	28		T2	992		T3	63
valid_sources[0x67]	400605	1		T1	35		T2	1110		T3	75
valid_sources[0x68]	402625	1		T1	39		T2	971		T3	43
valid_sources[0x69]	404638	1		T1	35		T2	1055		T3	88
valid_sources[0x6a]	399557	1		T1	17		T2	960		T3	76
valid_sources[0x6b]	402551	1		T1	7		T2	999		T3	59
valid_sources[0x6c]	399116	1		T1	56		T2	1098		T3	68
valid_sources[0x6d]	398373	1		T1	52		T2	1037		T3	68
valid_sources[0x6e]	398992	1		T1	8		T2	1038		T3	79
valid_sources[0x6f]	401460	1		T1	44		T2	1003		T3	80
valid_sources[0x70]	404244	1		T1	25		T2	1003		T3	85
valid_sources[0x71]	398647	1		T1	27		T2	975		T3	79
valid_sources[0x72]	402667	1		T1	43		T2	919		T3	97
valid_sources[0x73]	405757	1		T1	21		T2	965		T3	71
valid_sources[0x74]	402228	1		T1	30		T2	1150		T3	92
valid_sources[0x75]	403336	1		T1	21		T2	966		T3	68
valid_sources[0x76]	401835	1		T1	3		T2	1120		T3	52
valid_sources[0x77]	1101195	1		T1	18		T2	978		T3	75
valid_sources[0x78]	446260	1		T1	30		T2	1014		T3	51
valid_sources[0x79]	398381	1		T1	5		T2	926		T3	77
valid_sources[0x7a]	399780	1		T1	36		T2	959		T3	84
valid_sources[0x7b]	402148	1		T1	14		T2	896		T3	73
valid_sources[0x7c]	394443	1		T1	27		T2	1046		T3	100
valid_sources[0x7d]	677620	1		T1	14		T2	1116		T3	68
valid_sources[0x7e]	403588	1		T1	21		T2	992		T3	68
valid_sources[0x7f]	399965	1		T1	13		T2	822		T3	44
valid_sources[0x80]	397945	1		T1	32		T2	987		T3	70

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67346559

1

T1

2978

T2

129414

T3

9510

values[0x0]

all_enables

biggest_size

606885

1

T1

19

T2

5

T3

14

values[0x1]

all_enables

biggest_size

604015

1

T1

10

T2

2

T3

19