Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2085028	0	0
cfg0_rd_A	2147483647	6711	0	0
compare_lower0_0_rd_A	2147483647	7431	0	0
compare_upper0_0_rd_A	2147483647	6830	0	0
ctrl_rd_A	2147483647	6642	0	0
intr_enable0_rd_A	2147483647	8317	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2085028	0	0
T10	676767	177323	0	0
T11	700208	0	0	0
T12	321943	0	0	0
T14	0	60792	0	0
T15	0	228357	0	0
T36	0	104685	0	0
T37	0	112968	0	0
T38	0	206023	0	0
T39	0	247964	0	0
T40	0	202060	0	0
T41	0	111489	0	0
T42	0	142479	0	0
T43	178666	0	0	0
T44	411049	0	0	0
T45	109812	0	0	0
T46	18949	0	0	0
T47	136156	0	0	0
T48	248407	0	0	0
T49	138166	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6711	0	0
T10	676767	1702	0	0
T11	700208	0	0	0
T12	321943	0	0	0
T14	0	555	0	0
T39	0	1334	0	0
T42	0	1671	0	0
T43	178666	0	0	0
T44	411049	0	0	0
T45	109812	0	0	0
T46	18949	0	0	0
T47	136156	0	0	0
T48	248407	0	0	0
T49	138166	0	0	0
T50	0	330	0	0
T51	0	43	0	0
T52	0	58	0	0
T53	0	9	0	0
T54	0	307	0	0
T55	0	66	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7431	0	0
T10	676767	2012	0	0
T11	700208	0	0	0
T12	321943	0	0	0
T14	0	675	0	0
T39	0	1576	0	0
T42	0	1766	0	0
T43	178666	0	0	0
T44	411049	0	0	0
T45	109812	0	0	0
T46	18949	0	0	0
T47	136156	0	0	0
T48	248407	0	0	0
T49	138166	0	0	0
T50	0	331	0	0
T51	0	18	0	0
T52	0	28	0	0
T53	0	15	0	0
T54	0	299	0	0
T55	0	64	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6830	0	0
T10	676767	2085	0	0
T11	700208	0	0	0
T12	321943	0	0	0
T14	0	563	0	0
T39	0	1311	0	0
T42	0	1625	0	0
T43	178666	0	0	0
T44	411049	0	0	0
T45	109812	0	0	0
T46	18949	0	0	0
T47	136156	0	0	0
T48	248407	0	0	0
T49	138166	0	0	0
T50	0	303	0	0
T51	0	15	0	0
T52	0	23	0	0
T53	0	11	0	0
T54	0	257	0	0
T55	0	58	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6642	0	0
T10	676767	1821	0	0
T11	700208	0	0	0
T12	321943	0	0	0
T14	0	683	0	0
T39	0	1308	0	0
T42	0	1514	0	0
T43	178666	0	0	0
T44	411049	0	0	0
T45	109812	0	0	0
T46	18949	0	0	0
T47	136156	0	0	0
T48	248407	0	0	0
T49	138166	0	0	0
T50	0	282	0	0
T51	0	31	0	0
T52	0	41	0	0
T53	0	7	0	0
T54	0	252	0	0
T55	0	47	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8317	0	0
T10	676767	1963	0	0
T11	700208	0	0	0
T12	321943	0	0	0
T14	0	849	0	0
T39	0	1586	0	0
T43	178666	0	0	0
T44	411049	0	0	0
T45	109812	0	0	0
T46	18949	0	0	0
T47	136156	0	0	0
T48	248407	0	0	0
T49	138166	0	0	0
T56	0	11	0	0
T57	0	35	0	0
T58	0	12	0	0
T59	0	111	0	0
T60	0	45	0	0
T61	0	18	0	0
T62	0	25	0	0