Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 74911236 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 75553087 1 T1 875 T2 4871 T3 2132



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 149909980 1 T1 1746 T2 9913 T3 4147
values[0x0] 263836 1 T1 16 T2 17 T3 3
values[0x1] 290507 1 T1 12 T2 22 T3 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 59849886 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 90614437 1 T1 1054 T2 5863 T3 2562



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 438977 1 T1 7 T3 13 T4 1973
valid_sources[0x01] 440792 1 T1 13 T3 12 T4 1949
valid_sources[0x02] 448666 1 T1 3 T3 18 T4 1945
valid_sources[0x03] 442509 1 T1 9 T3 14 T4 2011
valid_sources[0x04] 444709 1 T1 11 T3 19 T4 1884
valid_sources[0x05] 442698 1 T1 4 T3 18 T4 1930
valid_sources[0x06] 445074 1 T1 10 T3 23 T4 1918
valid_sources[0x07] 469531 1 T1 8 T3 9 T4 1800
valid_sources[0x08] 445399 1 T1 5 T3 18 T4 1953
valid_sources[0x09] 473961 1 T1 7 T3 15 T4 1987
valid_sources[0x0a] 494485 1 T1 6 T3 14 T4 1954
valid_sources[0x0b] 443405 1 T1 8 T3 21 T4 1875
valid_sources[0x0c] 441407 1 T1 3 T3 21 T4 2030
valid_sources[0x0d] 1254427 1 T1 19 T3 20 T4 1953
valid_sources[0x0e] 446236 1 T1 6 T3 10 T4 1865
valid_sources[0x0f] 1276215 1 T1 9 T3 16 T4 1940
valid_sources[0x10] 1747872 1 T1 15 T3 16 T4 1913
valid_sources[0x11] 439075 1 T1 12 T3 13 T4 1865
valid_sources[0x12] 440653 1 T1 4 T3 17 T4 1890
valid_sources[0x13] 669347 1 T1 5 T3 13 T4 1893
valid_sources[0x14] 439650 1 T1 10 T3 27 T4 1935
valid_sources[0x15] 947071 1 T1 5 T3 12 T4 1929
valid_sources[0x16] 436280 1 T1 4 T3 9 T4 1921
valid_sources[0x17] 437587 1 T1 3 T3 16 T4 1977
valid_sources[0x18] 441030 1 T1 3 T3 14 T4 1871
valid_sources[0x19] 442911 1 T1 14 T3 20 T4 1944
valid_sources[0x1a] 442436 1 T1 4 T3 12 T4 1979
valid_sources[0x1b] 3098349 1 T1 3 T3 18 T4 1922
valid_sources[0x1c] 3129008 1 T1 11 T3 13 T4 1785
valid_sources[0x1d] 435176 1 T1 2 T3 16 T4 1836
valid_sources[0x1e] 435557 1 T1 10 T3 19 T4 1931
valid_sources[0x1f] 441118 1 T1 6 T3 9 T4 1992
valid_sources[0x20] 440103 1 T1 10 T3 15 T4 1927
valid_sources[0x21] 468917 1 T1 5 T3 22 T4 1899
valid_sources[0x22] 637101 1 T1 6 T3 19 T4 1974
valid_sources[0x23] 671562 1 T1 3 T3 19 T4 1947
valid_sources[0x24] 441699 1 T1 9 T3 22 T4 1857
valid_sources[0x25] 437994 1 T1 5 T3 20 T4 1879
valid_sources[0x26] 446550 1 T3 19 T4 2021 T6 33
valid_sources[0x27] 439870 1 T1 8 T3 14 T4 1963
valid_sources[0x28] 471681 1 T1 5 T3 14 T4 1911
valid_sources[0x29] 441888 1 T1 10 T3 9 T4 1985
valid_sources[0x2a] 441843 1 T1 10 T3 11 T4 1975
valid_sources[0x2b] 439626 1 T1 5 T3 12 T4 1986
valid_sources[0x2c] 504843 1 T1 7 T3 21 T4 1869
valid_sources[0x2d] 440354 1 T1 1 T3 16 T4 1983
valid_sources[0x2e] 440281 1 T1 7 T3 11 T4 1945
valid_sources[0x2f] 443426 1 T1 2 T3 19 T4 1900
valid_sources[0x30] 439771 1 T1 12 T3 16 T4 1940
valid_sources[0x31] 437774 1 T1 8 T3 13 T4 2020
valid_sources[0x32] 519888 1 T1 6 T3 17 T4 1957
valid_sources[0x33] 1012015 1 T1 5 T3 11 T4 2032
valid_sources[0x34] 473059 1 T1 6 T3 13 T4 2032
valid_sources[0x35] 439779 1 T1 7 T3 20 T4 1850
valid_sources[0x36] 3295246 1 T1 2 T3 20 T4 1848
valid_sources[0x37] 443622 1 T1 4 T3 13 T4 1972
valid_sources[0x38] 439459 1 T1 5 T3 25 T4 1969
valid_sources[0x39] 442636 1 T1 10 T3 18 T4 1982
valid_sources[0x3a] 438665 1 T1 2 T3 11 T4 2003
valid_sources[0x3b] 439177 1 T1 9 T3 17 T4 1883
valid_sources[0x3c] 441296 1 T1 5 T3 22 T4 1921
valid_sources[0x3d] 441130 1 T1 5 T3 24 T4 1965
valid_sources[0x3e] 579445 1 T1 5 T3 14 T4 1834
valid_sources[0x3f] 436865 1 T1 6 T3 10 T4 1895
valid_sources[0x40] 439918 1 T1 15 T3 9 T4 2070
valid_sources[0x41] 439846 1 T1 10 T3 13 T4 1937
valid_sources[0x42] 877891 1 T1 8 T3 18 T4 2022
valid_sources[0x43] 438311 1 T1 10 T3 18 T4 1843
valid_sources[0x44] 1273189 1 T1 11 T3 15 T4 1898
valid_sources[0x45] 444952 1 T1 10 T3 11 T4 1949
valid_sources[0x46] 602591 1 T1 11 T3 14 T4 1967
valid_sources[0x47] 439017 1 T1 6 T3 14 T4 1928
valid_sources[0x48] 483136 1 T1 6 T3 18 T4 1892
valid_sources[0x49] 444637 1 T1 10 T3 17 T4 1875
valid_sources[0x4a] 437219 1 T1 6 T3 16 T4 1871
valid_sources[0x4b] 441220 1 T1 4 T3 15 T4 1939
valid_sources[0x4c] 551325 1 T1 11 T3 14 T4 1979
valid_sources[0x4d] 438726 1 T1 5 T3 8 T4 2016
valid_sources[0x4e] 531454 1 T1 7 T3 16 T4 2053
valid_sources[0x4f] 440797 1 T1 2 T3 15 T4 1933
valid_sources[0x50] 444516 1 T1 3 T2 9952 T3 20
valid_sources[0x51] 444150 1 T1 9 T3 7 T4 1905
valid_sources[0x52] 440581 1 T1 10 T3 13 T4 1962
valid_sources[0x53] 460786 1 T1 7 T3 13 T4 1928
valid_sources[0x54] 503678 1 T1 2 T3 13 T4 1981
valid_sources[0x55] 437436 1 T1 2 T3 11 T4 1797
valid_sources[0x56] 462123 1 T1 11 T3 17 T4 2053
valid_sources[0x57] 444390 1 T1 7 T3 19 T4 1893
valid_sources[0x58] 439295 1 T1 7 T3 18 T4 1959
valid_sources[0x59] 432953 1 T1 8 T3 22 T4 1879
valid_sources[0x5a] 440864 1 T1 3 T3 14 T4 1854
valid_sources[0x5b] 439491 1 T1 12 T3 17 T4 1981
valid_sources[0x5c] 441152 1 T1 7 T3 18 T4 2009
valid_sources[0x5d] 441374 1 T1 8 T3 10 T4 1861
valid_sources[0x5e] 443285 1 T1 7 T3 16 T4 1843
valid_sources[0x5f] 591525 1 T1 11 T3 20 T4 1920
valid_sources[0x60] 441081 1 T1 5 T3 22 T4 2006
valid_sources[0x61] 438541 1 T1 5 T3 11 T4 1916
valid_sources[0x62] 458657 1 T1 13 T3 16 T4 1857
valid_sources[0x63] 437729 1 T1 2 T3 15 T4 1840
valid_sources[0x64] 436325 1 T1 7 T3 15 T4 1963
valid_sources[0x65] 440419 1 T1 2 T3 15 T4 1967
valid_sources[0x66] 438841 1 T1 12 T3 14 T4 1930
valid_sources[0x67] 440345 1 T1 7 T3 27 T4 1881
valid_sources[0x68] 2050565 1 T1 5 T3 16 T4 2007
valid_sources[0x69] 440667 1 T1 2 T3 18 T4 1918
valid_sources[0x6a] 465697 1 T1 5 T3 16 T4 1985
valid_sources[0x6b] 438083 1 T1 11 T3 16 T4 1916
valid_sources[0x6c] 440092 1 T1 3 T3 11 T4 1955
valid_sources[0x6d] 441759 1 T1 8 T3 13 T4 1934
valid_sources[0x6e] 441284 1 T1 4 T3 11 T4 1898
valid_sources[0x6f] 441649 1 T1 4 T3 18 T4 1971
valid_sources[0x70] 443647 1 T1 10 T3 25 T4 1796
valid_sources[0x71] 438759 1 T1 10 T3 21 T4 1897
valid_sources[0x72] 442161 1 T3 11 T4 2019 T6 22
valid_sources[0x73] 440596 1 T1 4 T3 13 T4 1912
valid_sources[0x74] 436567 1 T1 5 T3 18 T4 1903
valid_sources[0x75] 438119 1 T1 6 T3 13 T4 1925
valid_sources[0x76] 1323955 1 T1 4 T3 14 T4 2072
valid_sources[0x77] 441835 1 T1 11 T3 26 T4 1965
valid_sources[0x78] 439985 1 T1 1 T3 17 T4 2095
valid_sources[0x79] 548425 1 T1 11 T3 16 T4 2002
valid_sources[0x7a] 438634 1 T1 5 T3 15 T4 1896
valid_sources[0x7b] 516561 1 T1 8 T3 15 T4 1823
valid_sources[0x7c] 472750 1 T1 4 T3 18 T4 1853
valid_sources[0x7d] 437191 1 T1 6 T3 14 T4 2025
valid_sources[0x7e] 1394098 1 T1 6 T3 14 T4 1825
valid_sources[0x7f] 441286 1 T1 6 T3 14 T4 1876
valid_sources[0x80] 552911 1 T1 3 T3 21 T4 1811



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 75042171 1 T1 855 T2 4842 T3 2127
values[0x0] all_enables biggest_size 256148 1 T1 11 T2 14 T3 3
values[0x1] all_enables biggest_size 254768 1 T1 9 T2 15 T3 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%