Module Definition
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Module : rv_timer_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_timer_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_timer_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.83 100.00 83.33 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_timer_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 2147483647 863754 0 0
cfg0_rd_A 2147483647 3004 0 0
compare_lower0_0_rd_A 2147483647 3099 0 0
compare_upper0_0_rd_A 2147483647 2847 0 0
ctrl_rd_A 2147483647 2981 0 0
intr_enable0_rd_A 2147483647 3950 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 863754 0 0
T12 129322 33047 0 0
T13 0 132397 0 0
T14 0 65935 0 0
T37 0 98844 0 0
T38 0 30546 0 0
T39 0 44019 0 0
T40 0 134260 0 0
T41 0 169930 0 0
T42 0 72975 0 0
T43 0 68325 0 0
T44 220670 0 0 0
T45 121426 0 0 0
T46 108912 0 0 0
T47 586754 0 0 0
T48 193144 0 0 0
T49 890999 0 0 0
T50 111130 0 0 0
T51 357396 0 0 0
T52 995070 0 0 0

cfg0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 3004 0 0
T12 129322 382 0 0
T31 0 64 0 0
T32 0 21 0 0
T33 0 434 0 0
T39 0 414 0 0
T41 0 921 0 0
T44 220670 0 0 0
T45 121426 0 0 0
T46 108912 0 0 0
T47 586754 0 0 0
T48 193144 0 0 0
T49 890999 0 0 0
T50 111130 0 0 0
T51 357396 0 0 0
T52 995070 0 0 0
T53 0 7 0 0
T54 0 4 0 0
T55 0 39 0 0
T56 0 61 0 0

compare_lower0_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 3099 0 0
T12 129322 400 0 0
T31 0 53 0 0
T32 0 13 0 0
T33 0 427 0 0
T39 0 502 0 0
T41 0 997 0 0
T44 220670 0 0 0
T45 121426 0 0 0
T46 108912 0 0 0
T47 586754 0 0 0
T48 193144 0 0 0
T49 890999 0 0 0
T50 111130 0 0 0
T51 357396 0 0 0
T52 995070 0 0 0
T53 0 4 0 0
T54 0 7 0 0
T56 0 39 0 0
T57 0 4 0 0

compare_upper0_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2847 0 0
T12 129322 317 0 0
T31 0 32 0 0
T32 0 13 0 0
T33 0 441 0 0
T39 0 500 0 0
T41 0 857 0 0
T44 220670 0 0 0
T45 121426 0 0 0
T46 108912 0 0 0
T47 586754 0 0 0
T48 193144 0 0 0
T49 890999 0 0 0
T50 111130 0 0 0
T51 357396 0 0 0
T52 995070 0 0 0
T54 0 8 0 0
T55 0 6 0 0
T56 0 49 0 0
T57 0 16 0 0

ctrl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2981 0 0
T12 129322 323 0 0
T31 0 38 0 0
T32 0 15 0 0
T33 0 452 0 0
T39 0 544 0 0
T41 0 866 0 0
T44 220670 0 0 0
T45 121426 0 0 0
T46 108912 0 0 0
T47 586754 0 0 0
T48 193144 0 0 0
T49 890999 0 0 0
T50 111130 0 0 0
T51 357396 0 0 0
T52 995070 0 0 0
T53 0 6 0 0
T54 0 2 0 0
T56 0 38 0 0
T57 0 9 0 0

intr_enable0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 3950 0 0
T12 129322 331 0 0
T24 0 26 0 0
T36 546966 48 0 0
T39 0 643 0 0
T44 220670 0 0 0
T45 121426 0 0 0
T46 108912 0 0 0
T47 586754 0 0 0
T58 0 22 0 0
T59 0 33 0 0
T60 0 11 0 0
T61 0 10 0 0
T62 0 36 0 0
T63 0 82 0 0
T64 113566 0 0 0
T65 392151 0 0 0
T66 465844 0 0 0
T67 728324 0 0 0

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