Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2196924	0	0
cfg0_rd_A	2147483647	9584	0	0
compare_lower0_0_rd_A	2147483647	10448	0	0
compare_upper0_0_rd_A	2147483647	9163	0	0
ctrl_rd_A	2147483647	9371	0	0
intr_enable0_rd_A	2147483647	11797	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2196924	0	0
T11	447375	131872	0	0
T12	743874	191833	0	0
T13	0	133621	0	0
T33	0	515267	0	0
T34	0	114535	0	0
T35	0	319103	0	0
T36	0	263373	0	0
T37	0	71470	0	0
T38	0	249403	0	0
T39	0	193655	0	0
T40	557780	0	0	0
T41	145839	0	0	0
T42	455649	0	0	0
T43	821488	0	0	0
T44	594209	0	0	0
T45	690256	0	0	0
T46	253804	0	0	0
T47	860443	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9584	0	0
T12	743874	2101	0	0
T13	0	1383	0	0
T29	0	132	0	0
T30	0	132	0	0
T31	0	14	0	0
T34	0	1146	0	0
T38	0	1153	0	0
T39	0	831	0	0
T48	0	7	0	0
T49	0	5	0	0
T50	883665	0	0	0
T51	107352	0	0	0
T52	142621	0	0	0
T53	946098	0	0	0
T54	949555	0	0	0
T55	604483	0	0	0
T56	154077	0	0	0
T57	211765	0	0	0
T58	932664	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10448	0	0
T12	743874	2231	0	0
T13	0	1565	0	0
T29	0	66	0	0
T30	0	97	0	0
T31	0	11	0	0
T34	0	1217	0	0
T38	0	1524	0	0
T39	0	1163	0	0
T48	0	2	0	0
T49	0	5	0	0
T50	883665	0	0	0
T51	107352	0	0	0
T52	142621	0	0	0
T53	946098	0	0	0
T54	949555	0	0	0
T55	604483	0	0	0
T56	154077	0	0	0
T57	211765	0	0	0
T58	932664	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9163	0	0
T12	743874	2013	0	0
T13	0	1261	0	0
T29	0	68	0	0
T30	0	102	0	0
T31	0	4	0	0
T34	0	1058	0	0
T38	0	1345	0	0
T39	0	1011	0	0
T49	0	1	0	0
T50	883665	0	0	0
T51	107352	0	0	0
T52	142621	0	0	0
T53	946098	0	0	0
T54	949555	0	0	0
T55	604483	0	0	0
T56	154077	0	0	0
T57	211765	0	0	0
T58	932664	0	0	0
T59	0	16	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9371	0	0
T12	743874	1866	0	0
T13	0	1245	0	0
T29	0	96	0	0
T30	0	69	0	0
T31	0	14	0	0
T34	0	1182	0	0
T38	0	1310	0	0
T39	0	1069	0	0
T48	0	10	0	0
T49	0	10	0	0
T50	883665	0	0	0
T51	107352	0	0	0
T52	142621	0	0	0
T53	946098	0	0	0
T54	949555	0	0	0
T55	604483	0	0	0
T56	154077	0	0	0
T57	211765	0	0	0
T58	932664	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11797	0	0
T8	499108	15	0	0
T9	417211	0	0	0
T10	357074	0	0	0
T11	447375	0	0	0
T12	0	2515	0	0
T13	0	1670	0	0
T40	557780	0	0	0
T41	145839	0	0	0
T42	455649	0	0	0
T43	821488	0	0	0
T60	0	55	0	0
T61	0	24	0	0
T62	0	18	0	0
T63	0	15	0	0
T64	0	26	0	0
T65	0	18	0	0
T66	0	14	0	0
T67	544645	0	0	0
T68	351560	0	0	0