Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	75457453	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	76442560	1		T1	127518		T2	1869		T3	11042

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	151029065	1		T1	254782		T2	3751		T3	22252
values[0x0]	414148	1		T1	93		T2	6		T3	8
values[0x1]	456800	1		T1	72		T2	7		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60281240	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	91618773	1		T1	153010		T2	2218		T3	13235

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	439019	1		T1	954		T2	10		T3	68
valid_sources[0x01]	443176	1		T1	1011		T2	17		T3	32
valid_sources[0x02]	442313	1		T1	975		T2	10		T3	105
valid_sources[0x03]	445405	1		T1	1006		T2	14		T3	103
valid_sources[0x04]	445951	1		T1	1019		T2	6		T3	79
valid_sources[0x05]	439582	1		T1	1027		T2	24		T3	116
valid_sources[0x06]	448649	1		T1	970		T2	9		T3	74
valid_sources[0x07]	556628	1		T1	903		T2	17		T3	97
valid_sources[0x08]	442650	1		T1	963		T2	16		T3	92
valid_sources[0x09]	497506	1		T1	959		T2	18		T3	74
valid_sources[0x0a]	443206	1		T1	951		T2	10		T3	93
valid_sources[0x0b]	2544015	1		T1	978		T2	12		T3	124
valid_sources[0x0c]	462809	1		T1	967		T2	11		T3	74
valid_sources[0x0d]	1568822	1		T1	947		T2	6		T3	50
valid_sources[0x0e]	696284	1		T1	990		T2	16		T3	101
valid_sources[0x0f]	446527	1		T1	1059		T2	21		T3	67
valid_sources[0x10]	445312	1		T1	966		T2	15		T3	58
valid_sources[0x11]	440544	1		T1	953		T2	18		T3	76
valid_sources[0x12]	442748	1		T1	1053		T2	17		T3	48
valid_sources[0x13]	443822	1		T1	1099		T2	12		T3	68
valid_sources[0x14]	446752	1		T1	1018		T2	16		T3	116
valid_sources[0x15]	734177	1		T1	1028		T2	18		T3	77
valid_sources[0x16]	442739	1		T1	990		T2	9		T3	48
valid_sources[0x17]	1257992	1		T1	1010		T2	26		T3	65
valid_sources[0x18]	442538	1		T1	935		T2	15		T3	101
valid_sources[0x19]	443561	1		T1	1041		T2	11		T3	122
valid_sources[0x1a]	444137	1		T1	1027		T2	24		T3	90
valid_sources[0x1b]	443519	1		T1	928		T2	14		T3	74
valid_sources[0x1c]	446830	1		T1	982		T2	16		T3	47
valid_sources[0x1d]	447148	1		T1	1016		T2	7		T3	56
valid_sources[0x1e]	440602	1		T1	915		T2	5		T3	51
valid_sources[0x1f]	444660	1		T1	974		T2	16		T3	87
valid_sources[0x20]	450826	1		T1	996		T2	16		T3	95
valid_sources[0x21]	3907501	1		T1	1033		T2	20		T3	100
valid_sources[0x22]	440280	1		T1	901		T2	14		T3	60
valid_sources[0x23]	441651	1		T1	993		T2	11		T3	146
valid_sources[0x24]	445608	1		T1	1001		T2	12		T3	78
valid_sources[0x25]	444973	1		T1	1000		T2	8		T3	148
valid_sources[0x26]	875592	1		T1	993		T2	8		T3	80
valid_sources[0x27]	439786	1		T1	1035		T2	15		T3	78
valid_sources[0x28]	439644	1		T1	985		T2	24		T3	113
valid_sources[0x29]	634667	1		T1	976		T2	26		T3	136
valid_sources[0x2a]	443894	1		T1	1014		T2	10		T3	64
valid_sources[0x2b]	443375	1		T1	955		T2	14		T3	110
valid_sources[0x2c]	451040	1		T1	1024		T2	16		T3	65
valid_sources[0x2d]	443049	1		T1	964		T2	30		T3	91
valid_sources[0x2e]	445353	1		T1	1080		T2	21		T3	120
valid_sources[0x2f]	656708	1		T1	970		T2	12		T3	63
valid_sources[0x30]	442706	1		T1	1024		T2	13		T3	108
valid_sources[0x31]	441091	1		T1	1063		T2	12		T3	112
valid_sources[0x32]	444138	1		T1	952		T2	22		T3	100
valid_sources[0x33]	444917	1		T1	1001		T2	16		T3	95
valid_sources[0x34]	444775	1		T1	930		T2	19		T3	99
valid_sources[0x35]	439191	1		T1	1010		T2	15		T3	100
valid_sources[0x36]	454554	1		T1	999		T2	19		T3	46
valid_sources[0x37]	442318	1		T1	1019		T2	12		T3	99
valid_sources[0x38]	1111688	1		T1	1082		T2	10		T3	124
valid_sources[0x39]	443191	1		T1	978		T2	12		T3	93
valid_sources[0x3a]	441023	1		T1	974		T2	12		T3	70
valid_sources[0x3b]	445865	1		T1	1017		T2	18		T3	109
valid_sources[0x3c]	441449	1		T1	1005		T2	2		T3	69
valid_sources[0x3d]	446127	1		T1	981		T2	23		T3	102
valid_sources[0x3e]	445773	1		T1	1003		T2	11		T3	80
valid_sources[0x3f]	664168	1		T1	1022		T2	9		T3	122
valid_sources[0x40]	500232	1		T1	917		T2	12		T3	59
valid_sources[0x41]	443703	1		T1	901		T2	6		T3	66
valid_sources[0x42]	444627	1		T1	975		T2	20		T3	113
valid_sources[0x43]	441632	1		T1	1017		T2	11		T3	53
valid_sources[0x44]	453584	1		T1	970		T2	22		T3	74
valid_sources[0x45]	441790	1		T1	1009		T2	13		T3	96
valid_sources[0x46]	440853	1		T1	941		T2	9		T3	74
valid_sources[0x47]	456412	1		T1	991		T2	13		T3	96
valid_sources[0x48]	442849	1		T1	983		T2	17		T3	56
valid_sources[0x49]	441538	1		T1	1045		T2	14		T3	78
valid_sources[0x4a]	1106727	1		T1	1041		T2	13		T3	104
valid_sources[0x4b]	446196	1		T1	931		T2	20		T3	102
valid_sources[0x4c]	470479	1		T1	1084		T2	12		T3	84
valid_sources[0x4d]	2759898	1		T1	996		T2	20		T3	112
valid_sources[0x4e]	1228405	1		T1	921		T2	22		T3	63
valid_sources[0x4f]	443768	1		T1	952		T2	16		T3	62
valid_sources[0x50]	443025	1		T1	965		T2	19		T3	85
valid_sources[0x51]	448965	1		T1	1058		T2	19		T3	104
valid_sources[0x52]	445913	1		T1	1051		T2	24		T3	132
valid_sources[0x53]	456376	1		T1	1079		T2	8		T3	73
valid_sources[0x54]	441587	1		T1	1050		T2	8		T3	79
valid_sources[0x55]	443273	1		T1	995		T2	8		T3	98
valid_sources[0x56]	442977	1		T1	947		T2	13		T3	71
valid_sources[0x57]	536433	1		T1	963		T2	11		T3	45
valid_sources[0x58]	443953	1		T1	949		T2	16		T3	92
valid_sources[0x59]	443740	1		T1	958		T2	15		T3	140
valid_sources[0x5a]	447755	1		T1	950		T2	4		T3	123
valid_sources[0x5b]	447863	1		T1	927		T2	17		T3	104
valid_sources[0x5c]	444334	1		T1	1018		T2	17		T3	63
valid_sources[0x5d]	441776	1		T1	995		T2	12		T3	136
valid_sources[0x5e]	449102	1		T1	964		T2	15		T3	56
valid_sources[0x5f]	445118	1		T1	973		T2	11		T3	97
valid_sources[0x60]	723255	1		T1	1009		T2	12		T3	82
valid_sources[0x61]	770478	1		T1	945		T2	16		T3	87
valid_sources[0x62]	443967	1		T1	950		T2	14		T3	120
valid_sources[0x63]	500454	1		T1	1032		T2	23		T3	96
valid_sources[0x64]	444355	1		T1	1026		T2	21		T3	136
valid_sources[0x65]	446098	1		T1	1067		T2	13		T3	58
valid_sources[0x66]	445578	1		T1	1062		T2	12		T3	95
valid_sources[0x67]	1089621	1		T1	1013		T2	19		T3	77
valid_sources[0x68]	543899	1		T1	999		T2	15		T3	97
valid_sources[0x69]	442971	1		T1	941		T2	18		T3	95
valid_sources[0x6a]	443906	1		T1	1008		T2	7		T3	76
valid_sources[0x6b]	2462221	1		T1	954		T2	25		T3	82
valid_sources[0x6c]	441625	1		T1	1020		T2	8		T3	74
valid_sources[0x6d]	441268	1		T1	1012		T2	18		T3	67
valid_sources[0x6e]	445239	1		T1	996		T2	9		T3	101
valid_sources[0x6f]	830078	1		T1	1076		T2	9		T3	88
valid_sources[0x70]	445638	1		T1	1034		T2	8		T3	124
valid_sources[0x71]	441476	1		T1	1040		T2	7		T3	111
valid_sources[0x72]	445383	1		T1	939		T2	16		T3	94
valid_sources[0x73]	444201	1		T1	950		T2	11		T3	93
valid_sources[0x74]	442254	1		T1	922		T2	18		T3	59
valid_sources[0x75]	444116	1		T1	1035		T2	9		T3	65
valid_sources[0x76]	445726	1		T1	1087		T2	19		T3	95
valid_sources[0x77]	439498	1		T1	1021		T2	17		T3	115
valid_sources[0x78]	440209	1		T1	974		T2	19		T3	105
valid_sources[0x79]	1564010	1		T1	949		T2	11		T3	93
valid_sources[0x7a]	446693	1		T1	1042		T2	22		T3	86
valid_sources[0x7b]	439183	1		T1	1025		T2	13		T3	98
valid_sources[0x7c]	437396	1		T1	942		T2	9		T3	109
valid_sources[0x7d]	442539	1		T1	1027		T2	26		T3	110
valid_sources[0x7e]	953751	1		T1	990		T2	12		T3	68
valid_sources[0x7f]	1297256	1		T1	943		T2	21		T3	124
valid_sources[0x80]	442561	1		T1	983		T2	15		T3	84

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75634020

1

T1

127393

T2

1860

T3

11027

values[0x0]

all_enables

biggest_size

405077

1

T1

78

T2

4

T3

6

values[0x1]

all_enables

biggest_size

403463

1

T1

47

T2

5

T3

9