Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1406869	0	0
cfg0_rd_A	2147483647	7102	0	0
compare_lower0_0_rd_A	2147483647	7690	0	0
compare_upper0_0_rd_A	2147483647	6759	0	0
ctrl_rd_A	2147483647	7082	0	0
intr_enable0_rd_A	2147483647	8775	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1406869	0	0
T15	283481	116767	0	0
T16	0	227991	0	0
T17	0	61610	0	0
T28	0	153449	0	0
T38	0	67230	0	0
T39	0	231839	0	0
T40	0	54042	0	0
T41	0	32604	0	0
T42	0	55403	0	0
T43	0	46184	0	0
T44	164822	0	0	0
T45	243844	0	0	0
T46	371309	0	0	0
T47	131517	0	0	0
T48	8681	0	0	0
T49	531012	0	0	0
T50	166312	0	0	0
T51	754957	0	0	0
T52	170134	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7102	0	0
T18	8051	0	0	0
T19	10640	0	0	0
T23	180777	0	0	0
T24	697676	0	0	0
T28	0	831	0	0
T31	0	124	0	0
T35	0	36	0	0
T36	0	4	0	0
T39	104026	2330	0	0
T41	0	344	0	0
T42	0	593	0	0
T53	0	750	0	0
T54	0	686	0	0
T55	0	10	0	0
T56	277185	0	0	0
T57	444342	0	0	0
T58	837865	0	0	0
T59	484719	0	0	0
T60	150387	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7690	0	0
T18	8051	0	0	0
T19	10640	0	0	0
T23	180777	0	0	0
T24	697676	0	0	0
T28	0	953	0	0
T31	0	101	0	0
T35	0	50	0	0
T36	0	7	0	0
T39	104026	2716	0	0
T41	0	399	0	0
T42	0	736	0	0
T53	0	757	0	0
T54	0	804	0	0
T56	277185	0	0	0
T57	444342	0	0	0
T58	837865	0	0	0
T59	484719	0	0	0
T60	150387	0	0	0
T61	0	7	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6759	0	0
T18	8051	0	0	0
T19	10640	0	0	0
T23	180777	0	0	0
T24	697676	0	0	0
T28	0	744	0	0
T31	0	91	0	0
T35	0	16	0	0
T39	104026	2408	0	0
T41	0	340	0	0
T42	0	594	0	0
T53	0	621	0	0
T54	0	716	0	0
T56	277185	0	0	0
T57	444342	0	0	0
T58	837865	0	0	0
T59	484719	0	0	0
T60	150387	0	0	0
T61	0	3	0	0
T62	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7082	0	0
T18	8051	0	0	0
T19	10640	0	0	0
T23	180777	0	0	0
T24	697676	0	0	0
T28	0	800	0	0
T31	0	77	0	0
T35	0	24	0	0
T39	104026	2777	0	0
T41	0	382	0	0
T42	0	462	0	0
T53	0	659	0	0
T54	0	605	0	0
T56	277185	0	0	0
T57	444342	0	0	0
T58	837865	0	0	0
T59	484719	0	0	0
T60	150387	0	0	0
T61	0	1	0	0
T63	0	9	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8775	0	0
T1	406611	16	0	0
T2	645311	0	0	0
T3	885157	0	0	0
T4	163650	0	0	0
T5	657185	0	0	0
T6	121177	0	0	0
T7	488293	0	0	0
T8	363071	0	0	0
T9	100824	0	0	0
T10	793660	0	0	0
T28	0	1086	0	0
T39	0	2970	0	0
T41	0	494	0	0
T42	0	707	0	0
T53	0	724	0	0
T54	0	810	0	0
T64	0	27	0	0
T65	0	20	0	0
T66	0	109	0	0