Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2192772	0	0
cfg0_rd_A	2147483647	4342	0	0
compare_lower0_0_rd_A	2147483647	4612	0	0
compare_upper0_0_rd_A	2147483647	4058	0	0
ctrl_rd_A	2147483647	4050	0	0
intr_enable0_rd_A	2147483647	5475	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2192772	0	0
T12	966124	40632	0	0
T13	0	121066	0	0
T14	0	23929	0	0
T32	0	46649	0	0
T33	0	39183	0	0
T34	0	336622	0	0
T35	0	273196	0	0
T36	0	32013	0	0
T37	0	179593	0	0
T38	0	181731	0	0
T39	150826	0	0	0
T40	892926	0	0	0
T41	106523	0	0	0
T42	588243	0	0	0
T43	289981	0	0	0
T44	433748	0	0	0
T45	116455	0	0	0
T46	614309	0	0	0
T47	282158	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4342	0	0
T27	0	638	0	0
T29	0	6	0	0
T32	178979	494	0	0
T35	0	1471	0	0
T36	0	353	0	0
T48	0	2	0	0
T49	0	5	0	0
T50	0	8	0	0
T51	0	5	0	0
T52	0	18	0	0
T53	23204	0	0	0
T54	133183	0	0	0
T55	195935	0	0	0
T56	120995	0	0	0
T57	136573	0	0	0
T58	276975	0	0	0
T59	124432	0	0	0
T60	437044	0	0	0
T61	108958	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4612	0	0
T27	0	663	0	0
T29	0	12	0	0
T32	178979	555	0	0
T35	0	1710	0	0
T36	0	374	0	0
T48	0	7	0	0
T49	0	8	0	0
T50	0	15	0	0
T51	0	14	0	0
T53	23204	0	0	0
T54	133183	0	0	0
T55	195935	0	0	0
T56	120995	0	0	0
T57	136573	0	0	0
T58	276975	0	0	0
T59	124432	0	0	0
T60	437044	0	0	0
T61	108958	0	0	0
T62	0	5	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4058	0	0
T27	0	667	0	0
T29	0	8	0	0
T32	178979	439	0	0
T35	0	1432	0	0
T36	0	295	0	0
T48	0	7	0	0
T49	0	8	0	0
T50	0	2	0	0
T51	0	12	0	0
T52	0	9	0	0
T53	23204	0	0	0
T54	133183	0	0	0
T55	195935	0	0	0
T56	120995	0	0	0
T57	136573	0	0	0
T58	276975	0	0	0
T59	124432	0	0	0
T60	437044	0	0	0
T61	108958	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4050	0	0
T27	0	630	0	0
T29	0	20	0	0
T32	178979	436	0	0
T35	0	1474	0	0
T36	0	358	0	0
T48	0	8	0	0
T49	0	2	0	0
T50	0	7	0	0
T51	0	11	0	0
T52	0	1	0	0
T53	23204	0	0	0
T54	133183	0	0	0
T55	195935	0	0	0
T56	120995	0	0	0
T57	136573	0	0	0
T58	276975	0	0	0
T59	124432	0	0	0
T60	437044	0	0	0
T61	108958	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5475	0	0
T32	178979	587	0	0
T35	0	1545	0	0
T36	0	356	0	0
T53	23204	0	0	0
T54	133183	0	0	0
T55	195935	0	0	0
T56	120995	0	0	0
T57	136573	0	0	0
T58	276975	0	0	0
T59	124432	0	0	0
T60	437044	0	0	0
T61	108958	0	0	0
T63	0	60	0	0
T64	0	59	0	0
T65	0	56	0	0
T66	0	39	0	0
T67	0	22	0	0
T68	0	22	0	0
T69	0	116	0	0