Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	143901	0	0
cfg0_rd_A	2147483647	2256	0	0
compare_lower0_0_rd_A	2147483647	1984	0	0
compare_upper0_0_rd_A	2147483647	2040	0	0
ctrl_rd_A	2147483647	1903	0	0
intr_enable0_rd_A	2147483647	2966	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	143901	0	0
T13	155620	4137	0	0
T14	0	9449	0	0
T15	0	8077	0	0
T37	0	5819	0	0
T38	0	4204	0	0
T39	0	4200	0	0
T40	0	26675	0	0
T41	0	9525	0	0
T42	0	394	0	0
T43	0	3361	0	0
T44	456543	0	0	0
T45	127256	0	0	0
T46	159783	0	0	0
T47	709703	0	0	0
T48	120417	0	0	0
T49	969220	0	0	0
T50	10037	0	0	0
T51	793211	0	0	0
T52	743369	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2256	0	0
T13	155620	51	0	0
T14	0	108	0	0
T37	0	106	0	0
T38	0	24	0	0
T41	0	131	0	0
T43	0	71	0	0
T44	456543	0	0	0
T45	127256	0	0	0
T46	159783	0	0	0
T47	709703	0	0	0
T48	120417	0	0	0
T49	969220	0	0	0
T50	10037	0	0	0
T51	793211	0	0	0
T52	743369	0	0	0
T53	0	218	0	0
T54	0	59	0	0
T55	0	61	0	0
T56	0	17	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1984	0	0
T13	155620	71	0	0
T14	0	195	0	0
T37	0	63	0	0
T38	0	46	0	0
T41	0	131	0	0
T43	0	44	0	0
T44	456543	0	0	0
T45	127256	0	0	0
T46	159783	0	0	0
T47	709703	0	0	0
T48	120417	0	0	0
T49	969220	0	0	0
T50	10037	0	0	0
T51	793211	0	0	0
T52	743369	0	0	0
T53	0	236	0	0
T54	0	39	0	0
T55	0	19	0	0
T57	0	35	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2040	0	0
T13	155620	51	0	0
T14	0	145	0	0
T37	0	55	0	0
T38	0	35	0	0
T41	0	157	0	0
T43	0	61	0	0
T44	456543	0	0	0
T45	127256	0	0	0
T46	159783	0	0	0
T47	709703	0	0	0
T48	120417	0	0	0
T49	969220	0	0	0
T50	10037	0	0	0
T51	793211	0	0	0
T52	743369	0	0	0
T53	0	204	0	0
T54	0	77	0	0
T55	0	75	0	0
T56	0	4	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1903	0	0
T13	155620	46	0	0
T14	0	134	0	0
T37	0	96	0	0
T38	0	57	0	0
T41	0	102	0	0
T43	0	44	0	0
T44	456543	0	0	0
T45	127256	0	0	0
T46	159783	0	0	0
T47	709703	0	0	0
T48	120417	0	0	0
T49	969220	0	0	0
T50	10037	0	0	0
T51	793211	0	0	0
T52	743369	0	0	0
T53	0	128	0	0
T54	0	54	0	0
T55	0	53	0	0
T57	0	29	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2966	0	0
T4	144367	4	0	0
T5	365839	0	0	0
T6	817315	0	0	0
T7	111192	0	0	0
T8	874636	0	0	0
T9	274736	0	0	0
T10	734605	0	0	0
T11	281780	0	0	0
T13	0	74	0	0
T14	0	247	0	0
T37	0	119	0	0
T38	0	26	0	0
T41	0	360	0	0
T43	0	66	0	0
T58	0	15	0	0
T59	0	93	0	0
T60	0	66	0	0
T61	648838	0	0	0
T62	188231	0	0	0