Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	134170	0	0
cfg0_rd_A	2147483647	2311	0	0
compare_lower0_0_rd_A	2147483647	1902	0	0
compare_upper0_0_rd_A	2147483647	1843	0	0
ctrl_rd_A	2147483647	1707	0	0
intr_enable0_rd_A	2147483647	3408	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	134170	0	0
T10	258963	6730	0	0
T11	0	4752	0	0
T12	0	5038	0	0
T32	0	15214	0	0
T33	0	9642	0	0
T34	0	18864	0	0
T35	0	3811	0	0
T36	0	5651	0	0
T37	0	4538	0	0
T38	0	5446	0	0
T39	779494	0	0	0
T40	123269	0	0	0
T41	122914	0	0	0
T42	298253	0	0	0
T43	358473	0	0	0
T44	433880	0	0	0
T45	175691	0	0	0
T46	964713	0	0	0
T47	634871	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2311	0	0
T10	258963	124	0	0
T11	0	68	0	0
T12	0	77	0	0
T32	0	225	0	0
T35	0	52	0	0
T39	779494	0	0	0
T40	123269	0	0	0
T41	122914	0	0	0
T42	298253	0	0	0
T43	358473	0	0	0
T44	433880	0	0	0
T45	175691	0	0	0
T46	964713	0	0	0
T47	634871	0	0	0
T48	0	154	0	0
T49	0	22	0	0
T50	0	8	0	0
T51	0	23	0	0
T52	0	95	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1902	0	0
T10	258963	73	0	0
T11	0	31	0	0
T12	0	67	0	0
T32	0	201	0	0
T35	0	51	0	0
T39	779494	0	0	0
T40	123269	0	0	0
T41	122914	0	0	0
T42	298253	0	0	0
T43	358473	0	0	0
T44	433880	0	0	0
T45	175691	0	0	0
T46	964713	0	0	0
T47	634871	0	0	0
T48	0	179	0	0
T49	0	18	0	0
T51	0	32	0	0
T52	0	45	0	0
T53	0	5	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1843	0	0
T10	258963	113	0	0
T11	0	14	0	0
T12	0	77	0	0
T32	0	151	0	0
T35	0	40	0	0
T39	779494	0	0	0
T40	123269	0	0	0
T41	122914	0	0	0
T42	298253	0	0	0
T43	358473	0	0	0
T44	433880	0	0	0
T45	175691	0	0	0
T46	964713	0	0	0
T47	634871	0	0	0
T48	0	140	0	0
T49	0	30	0	0
T50	0	2	0	0
T51	0	22	0	0
T52	0	67	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1707	0	0
T10	258963	68	0	0
T11	0	26	0	0
T12	0	100	0	0
T32	0	169	0	0
T35	0	77	0	0
T39	779494	0	0	0
T40	123269	0	0	0
T41	122914	0	0	0
T42	298253	0	0	0
T43	358473	0	0	0
T44	433880	0	0	0
T45	175691	0	0	0
T46	964713	0	0	0
T47	634871	0	0	0
T48	0	154	0	0
T49	0	37	0	0
T50	0	1	0	0
T51	0	17	0	0
T52	0	19	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3408	0	0
T1	180664	70	0	0
T2	449973	0	0	0
T3	8470	0	0	0
T4	115147	0	0	0
T5	317200	0	0	0
T6	317990	0	0	0
T7	157988	0	0	0
T8	703214	0	0	0
T9	513359	0	0	0
T10	258963	221	0	0
T11	0	119	0	0
T12	0	161	0	0
T32	0	347	0	0
T35	0	197	0	0
T54	0	47	0	0
T55	0	70	0	0
T56	0	49	0	0
T57	0	3	0	0