Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58949144	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	59086252	1		T1	10183		T2	6378		T3	147462

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	117900445	1		T1	20296		T2	12772		T3	295186
values[0x0]	65184	1		T1	2		T2	7		T3	5
values[0x1]	69767	1		T1	12		T2	3		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47102724	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	70932672	1		T1	12264		T2	7661		T3	177172

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	374813	1		T1	98		T2	24		T3	1115
valid_sources[0x01]	371748	1		T1	72		T2	67		T3	1274
valid_sources[0x02]	375068	1		T1	67		T2	62		T3	1100
valid_sources[0x03]	523796	1		T1	81		T2	56		T3	1129
valid_sources[0x04]	373831	1		T1	84		T2	42		T3	1190
valid_sources[0x05]	374459	1		T1	65		T2	74		T3	1244
valid_sources[0x06]	374901	1		T1	78		T2	38		T3	1233
valid_sources[0x07]	375360	1		T1	77		T2	59		T3	1215
valid_sources[0x08]	373192	1		T1	65		T2	38		T3	1076
valid_sources[0x09]	381456	1		T1	64		T2	54		T3	1102
valid_sources[0x0a]	373352	1		T1	71		T2	61		T3	1199
valid_sources[0x0b]	372891	1		T1	76		T2	52		T3	1171
valid_sources[0x0c]	373831	1		T1	68		T2	78		T3	1212
valid_sources[0x0d]	374398	1		T1	84		T2	47		T3	1191
valid_sources[0x0e]	589012	1		T1	84		T2	37		T3	1168
valid_sources[0x0f]	371107	1		T1	91		T2	41		T3	1142
valid_sources[0x10]	380933	1		T1	60		T2	60		T3	1147
valid_sources[0x11]	374895	1		T1	62		T2	28		T3	1133
valid_sources[0x12]	373176	1		T1	83		T2	59		T3	1161
valid_sources[0x13]	374437	1		T1	85		T2	53		T3	1166
valid_sources[0x14]	394473	1		T1	70		T2	56		T3	1178
valid_sources[0x15]	3423690	1		T1	66		T2	35		T3	1182
valid_sources[0x16]	2367179	1		T1	85		T2	48		T3	1152
valid_sources[0x17]	373605	1		T1	83		T2	37		T3	1317
valid_sources[0x18]	373315	1		T1	95		T2	51		T3	1144
valid_sources[0x19]	374069	1		T1	101		T2	67		T3	1099
valid_sources[0x1a]	376450	1		T1	78		T2	43		T3	1217
valid_sources[0x1b]	391319	1		T1	67		T2	62		T3	1322
valid_sources[0x1c]	374668	1		T1	112		T2	67		T3	1207
valid_sources[0x1d]	374990	1		T1	66		T2	38		T3	1275
valid_sources[0x1e]	372042	1		T1	65		T2	37		T3	1163
valid_sources[0x1f]	373482	1		T1	67		T2	47		T3	1151
valid_sources[0x20]	373119	1		T1	83		T2	35		T3	1260
valid_sources[0x21]	372080	1		T1	76		T2	57		T3	1115
valid_sources[0x22]	426993	1		T1	79		T2	42		T3	1129
valid_sources[0x23]	372838	1		T1	63		T2	36		T3	1132
valid_sources[0x24]	372129	1		T1	83		T2	60		T3	1157
valid_sources[0x25]	372507	1		T1	61		T2	40		T3	1077
valid_sources[0x26]	373712	1		T1	88		T2	48		T3	1136
valid_sources[0x27]	373745	1		T1	101		T2	54		T3	1121
valid_sources[0x28]	377143	1		T1	96		T2	50		T3	1125
valid_sources[0x29]	373054	1		T1	83		T2	53		T3	1236
valid_sources[0x2a]	372985	1		T1	77		T2	68		T3	1122
valid_sources[0x2b]	373025	1		T1	87		T2	17		T3	1132
valid_sources[0x2c]	372669	1		T1	67		T2	48		T3	1109
valid_sources[0x2d]	372908	1		T1	78		T2	46		T3	1079
valid_sources[0x2e]	383495	1		T1	71		T2	93		T3	1157
valid_sources[0x2f]	374081	1		T1	79		T2	43		T3	1198
valid_sources[0x30]	394473	1		T1	77		T2	24		T3	1164
valid_sources[0x31]	375073	1		T1	86		T2	61		T3	1107
valid_sources[0x32]	371168	1		T1	71		T2	16		T3	1153
valid_sources[0x33]	374701	1		T1	77		T2	73		T3	1168
valid_sources[0x34]	371518	1		T1	70		T2	27		T3	985
valid_sources[0x35]	427976	1		T1	74		T2	87		T3	1167
valid_sources[0x36]	373080	1		T1	81		T2	58		T3	1104
valid_sources[0x37]	372443	1		T1	70		T2	45		T3	1102
valid_sources[0x38]	374496	1		T1	83		T2	40		T3	1102
valid_sources[0x39]	495892	1		T1	69		T2	44		T3	1164
valid_sources[0x3a]	381305	1		T1	81		T2	45		T3	1174
valid_sources[0x3b]	375091	1		T1	92		T2	42		T3	1127
valid_sources[0x3c]	372136	1		T1	110		T2	45		T3	1248
valid_sources[0x3d]	377288	1		T1	84		T2	49		T3	1087
valid_sources[0x3e]	376184	1		T1	78		T2	81		T3	1192
valid_sources[0x3f]	441634	1		T1	80		T2	25		T3	1225
valid_sources[0x40]	376215	1		T1	75		T2	49		T3	1163
valid_sources[0x41]	1533999	1		T1	81		T2	51		T3	1113
valid_sources[0x42]	375300	1		T1	73		T2	54		T3	1178
valid_sources[0x43]	589364	1		T1	76		T2	47		T3	1107
valid_sources[0x44]	462412	1		T1	63		T2	33		T3	1172
valid_sources[0x45]	703892	1		T1	78		T2	47		T3	1177
valid_sources[0x46]	493938	1		T1	67		T2	28		T3	1240
valid_sources[0x47]	385045	1		T1	89		T2	38		T3	1119
valid_sources[0x48]	374192	1		T1	76		T2	68		T3	1187
valid_sources[0x49]	374299	1		T1	62		T2	57		T3	1142
valid_sources[0x4a]	376777	1		T1	68		T2	24		T3	1210
valid_sources[0x4b]	452937	1		T1	79		T2	65		T3	1142
valid_sources[0x4c]	373824	1		T1	88		T2	78		T3	1177
valid_sources[0x4d]	373849	1		T1	71		T2	48		T3	1270
valid_sources[0x4e]	373677	1		T1	118		T2	39		T3	1082
valid_sources[0x4f]	369767	1		T1	76		T2	56		T3	1188
valid_sources[0x50]	375063	1		T1	86		T2	59		T3	1099
valid_sources[0x51]	372177	1		T1	80		T2	33		T3	1171
valid_sources[0x52]	373205	1		T1	77		T2	27		T3	1103
valid_sources[0x53]	3266207	1		T1	80		T2	63		T3	1203
valid_sources[0x54]	380765	1		T1	96		T2	47		T3	1038
valid_sources[0x55]	1005449	1		T1	60		T2	46		T3	1176
valid_sources[0x56]	388370	1		T1	95		T2	70		T3	1170
valid_sources[0x57]	373712	1		T1	74		T2	34		T3	1141
valid_sources[0x58]	372634	1		T1	80		T2	29		T3	1210
valid_sources[0x59]	373872	1		T1	83		T2	65		T3	1205
valid_sources[0x5a]	375719	1		T1	72		T2	46		T3	1214
valid_sources[0x5b]	373020	1		T1	83		T2	70		T3	1037
valid_sources[0x5c]	375054	1		T1	69		T2	33		T3	1162
valid_sources[0x5d]	375329	1		T1	56		T2	46		T3	1135
valid_sources[0x5e]	375373	1		T1	101		T2	31		T3	1238
valid_sources[0x5f]	376710	1		T1	84		T2	85		T3	1216
valid_sources[0x60]	373797	1		T1	73		T2	31		T3	1212
valid_sources[0x61]	373162	1		T1	94		T2	54		T3	1162
valid_sources[0x62]	373528	1		T1	80		T2	50		T3	1122
valid_sources[0x63]	371892	1		T1	63		T2	60		T3	1103
valid_sources[0x64]	681089	1		T1	78		T2	25		T3	1256
valid_sources[0x65]	719382	1		T1	82		T2	49		T3	1147
valid_sources[0x66]	374920	1		T1	75		T2	29		T3	1122
valid_sources[0x67]	371622	1		T1	78		T2	23		T3	1037
valid_sources[0x68]	372242	1		T1	75		T2	41		T3	1196
valid_sources[0x69]	374822	1		T1	81		T2	29		T3	1198
valid_sources[0x6a]	372132	1		T1	74		T2	57		T3	1194
valid_sources[0x6b]	374656	1		T1	88		T2	39		T3	1200
valid_sources[0x6c]	373294	1		T1	84		T2	34		T3	1259
valid_sources[0x6d]	374654	1		T1	77		T2	47		T3	1210
valid_sources[0x6e]	374285	1		T1	68		T2	76		T3	1144
valid_sources[0x6f]	1199087	1		T1	81		T2	24		T3	1120
valid_sources[0x70]	374168	1		T1	76		T2	31		T3	1127
valid_sources[0x71]	532521	1		T1	66		T2	38		T3	1127
valid_sources[0x72]	376151	1		T1	97		T2	10		T3	1091
valid_sources[0x73]	374857	1		T1	93		T2	30		T3	1122
valid_sources[0x74]	373043	1		T1	93		T2	40		T3	1214
valid_sources[0x75]	373525	1		T1	100		T2	39		T3	1133
valid_sources[0x76]	374116	1		T1	74		T2	97		T3	1128
valid_sources[0x77]	374548	1		T1	92		T2	19		T3	1082
valid_sources[0x78]	371149	1		T1	97		T2	24		T3	1050
valid_sources[0x79]	376144	1		T1	75		T2	39		T3	1127
valid_sources[0x7a]	376408	1		T1	84		T2	68		T3	1124
valid_sources[0x7b]	374108	1		T1	87		T2	57		T3	1100
valid_sources[0x7c]	373103	1		T1	90		T2	55		T3	1147
valid_sources[0x7d]	404111	1		T1	74		T2	52		T3	1172
valid_sources[0x7e]	374564	1		T1	91		T2	63		T3	1115
valid_sources[0x7f]	372368	1		T1	86		T2	69		T3	1293
valid_sources[0x80]	806329	1		T1	64		T2	67		T3	1150

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

58968644

1

T1

10173

T2

6370

T3

147456

values[0x0]

all_enables

biggest_size

59799

1

T1

2

T2

6

T3

3

values[0x1]

all_enables

biggest_size

57809

1

T1

8

T2

2

T3

3