Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	162965	0	0
cfg0_rd_A	2147483647	2363	0	0
compare_lower0_0_rd_A	2147483647	2494	0	0
compare_upper0_0_rd_A	2147483647	2416	0	0
ctrl_rd_A	2147483647	2291	0	0
intr_enable0_rd_A	2147483647	3398	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	162965	0	0
T11	119562	3699	0	0
T12	111937	0	0	0
T13	143185	0	0	0
T14	0	12085	0	0
T15	0	6941	0	0
T34	0	5714	0	0
T35	0	8571	0	0
T36	0	13098	0	0
T37	0	7757	0	0
T38	0	8767	0	0
T39	0	11490	0	0
T40	0	7804	0	0
T41	256152	0	0	0
T42	7456	0	0	0
T43	259098	0	0	0
T44	985535	0	0	0
T45	103071	0	0	0
T46	100352	0	0	0
T47	127215	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2363	0	0
T11	119562	43	0	0
T12	111937	0	0	0
T13	143185	0	0	0
T14	0	99	0	0
T33	0	669	0	0
T34	0	32	0	0
T38	0	81	0	0
T40	0	109	0	0
T41	256152	0	0	0
T42	7456	0	0	0
T43	259098	0	0	0
T44	985535	0	0	0
T45	103071	0	0	0
T46	100352	0	0	0
T47	127215	0	0	0
T48	0	42	0	0
T49	0	8	0	0
T50	0	47	0	0
T51	0	12	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2494	0	0
T11	119562	81	0	0
T12	111937	0	0	0
T13	143185	0	0	0
T14	0	162	0	0
T33	0	643	0	0
T34	0	61	0	0
T38	0	142	0	0
T40	0	114	0	0
T41	256152	0	0	0
T42	7456	0	0	0
T43	259098	0	0	0
T44	985535	0	0	0
T45	103071	0	0	0
T46	100352	0	0	0
T47	127215	0	0	0
T48	0	93	0	0
T49	0	8	0	0
T50	0	36	0	0
T51	0	15	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2416	0	0
T11	119562	44	0	0
T12	111937	0	0	0
T13	143185	0	0	0
T14	0	147	0	0
T33	0	726	0	0
T34	0	45	0	0
T38	0	98	0	0
T40	0	136	0	0
T41	256152	0	0	0
T42	7456	0	0	0
T43	259098	0	0	0
T44	985535	0	0	0
T45	103071	0	0	0
T46	100352	0	0	0
T47	127215	0	0	0
T48	0	40	0	0
T49	0	8	0	0
T50	0	37	0	0
T52	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2291	0	0
T11	119562	55	0	0
T12	111937	0	0	0
T13	143185	0	0	0
T14	0	112	0	0
T33	0	651	0	0
T34	0	34	0	0
T38	0	100	0	0
T40	0	115	0	0
T41	256152	0	0	0
T42	7456	0	0	0
T43	259098	0	0	0
T44	985535	0	0	0
T45	103071	0	0	0
T46	100352	0	0	0
T47	127215	0	0	0
T48	0	122	0	0
T49	0	9	0	0
T50	0	33	0	0
T52	0	8	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3398	0	0
T11	119562	107	0	0
T12	111937	0	0	0
T13	143185	0	0	0
T14	0	243	0	0
T34	0	58	0	0
T38	0	281	0	0
T40	0	160	0	0
T41	256152	0	0	0
T42	7456	0	0	0
T43	259098	0	0	0
T44	985535	0	0	0
T45	103071	0	0	0
T46	100352	0	0	0
T47	127215	0	0	0
T53	0	22	0	0
T54	0	13	0	0
T55	0	19	0	0
T56	0	36	0	0
T57	0	8	0	0