Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	72727395	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	72837780	1		T1	66542		T2	4591		T3	11210

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	145454320	1		T1	133054		T2	9130		T3	22275
values[0x0]	53446	1		T1	72		T2	17		T3	20
values[0x1]	57409	1		T1	67		T2	16		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58121004	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	87444171	1		T1	80006		T2	5523		T3	13431

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	491207	1		T1	581		T2	46		T3	91
valid_sources[0x01]	486508	1		T1	509		T2	36		T3	139
valid_sources[0x02]	485247	1		T1	569		T2	41		T3	88
valid_sources[0x03]	490344	1		T1	486		T2	33		T3	74
valid_sources[0x04]	490711	1		T1	598		T2	24		T3	73
valid_sources[0x05]	490577	1		T1	539		T2	33		T3	110
valid_sources[0x06]	487473	1		T1	512		T2	36		T3	84
valid_sources[0x07]	486511	1		T1	572		T2	38		T3	71
valid_sources[0x08]	489578	1		T1	554		T2	38		T3	87
valid_sources[0x09]	551429	1		T1	494		T2	40		T3	107
valid_sources[0x0a]	483833	1		T1	600		T2	42		T3	99
valid_sources[0x0b]	488828	1		T1	522		T2	35		T3	72
valid_sources[0x0c]	493956	1		T1	531		T2	33		T3	83
valid_sources[0x0d]	489350	1		T1	454		T2	35		T3	115
valid_sources[0x0e]	491046	1		T1	524		T2	34		T3	65
valid_sources[0x0f]	484927	1		T1	554		T2	37		T3	87
valid_sources[0x10]	489345	1		T1	569		T2	37		T3	81
valid_sources[0x11]	491262	1		T1	480		T2	36		T3	58
valid_sources[0x12]	486823	1		T1	489		T2	30		T3	95
valid_sources[0x13]	488742	1		T1	513		T2	41		T3	96
valid_sources[0x14]	635529	1		T1	575		T2	32		T3	54
valid_sources[0x15]	493639	1		T1	500		T2	43		T3	67
valid_sources[0x16]	883278	1		T1	539		T2	42		T3	109
valid_sources[0x17]	491764	1		T1	598		T2	38		T3	82
valid_sources[0x18]	487210	1		T1	536		T2	41		T3	73
valid_sources[0x19]	488905	1		T1	501		T2	37		T3	81
valid_sources[0x1a]	488257	1		T1	463		T2	41		T3	82
valid_sources[0x1b]	488414	1		T1	504		T2	44		T3	79
valid_sources[0x1c]	487697	1		T1	589		T2	43		T3	72
valid_sources[0x1d]	487856	1		T1	573		T2	35		T3	99
valid_sources[0x1e]	718374	1		T1	571		T2	31		T3	87
valid_sources[0x1f]	488059	1		T1	469		T2	34		T3	89
valid_sources[0x20]	489257	1		T1	463		T2	43		T3	70
valid_sources[0x21]	493938	1		T1	451		T2	42		T3	117
valid_sources[0x22]	491587	1		T1	538		T2	42		T3	60
valid_sources[0x23]	486031	1		T1	576		T2	43		T3	89
valid_sources[0x24]	488199	1		T1	524		T2	30		T3	94
valid_sources[0x25]	485653	1		T1	496		T2	38		T3	71
valid_sources[0x26]	575475	1		T1	549		T2	41		T3	87
valid_sources[0x27]	485915	1		T1	549		T2	29		T3	66
valid_sources[0x28]	486726	1		T1	537		T2	34		T3	85
valid_sources[0x29]	489965	1		T1	547		T2	40		T3	71
valid_sources[0x2a]	489418	1		T1	484		T2	40		T3	88
valid_sources[0x2b]	490406	1		T1	463		T2	47		T3	83
valid_sources[0x2c]	542541	1		T1	494		T2	35		T3	114
valid_sources[0x2d]	490199	1		T1	598		T2	43		T3	77
valid_sources[0x2e]	485682	1		T1	557		T2	37		T3	83
valid_sources[0x2f]	488851	1		T1	542		T2	26		T3	77
valid_sources[0x30]	488564	1		T1	547		T2	33		T3	69
valid_sources[0x31]	486087	1		T1	536		T2	33		T3	86
valid_sources[0x32]	1868157	1		T1	458		T2	33		T3	99
valid_sources[0x33]	491586	1		T1	523		T2	45		T3	104
valid_sources[0x34]	497564	1		T1	482		T2	42		T3	58
valid_sources[0x35]	490295	1		T1	482		T2	43		T3	100
valid_sources[0x36]	485724	1		T1	506		T2	45		T3	104
valid_sources[0x37]	484953	1		T1	487		T2	36		T3	94
valid_sources[0x38]	786275	1		T1	426		T2	24		T3	108
valid_sources[0x39]	490133	1		T1	590		T2	32		T3	87
valid_sources[0x3a]	586275	1		T1	458		T2	36		T3	79
valid_sources[0x3b]	487750	1		T1	538		T2	38		T3	100
valid_sources[0x3c]	484146	1		T1	460		T2	36		T3	102
valid_sources[0x3d]	506161	1		T1	465		T2	39		T3	74
valid_sources[0x3e]	488262	1		T1	550		T2	29		T3	69
valid_sources[0x3f]	523030	1		T1	480		T2	37		T3	97
valid_sources[0x40]	486277	1		T1	454		T2	35		T3	91
valid_sources[0x41]	487574	1		T1	487		T2	38		T3	69
valid_sources[0x42]	487161	1		T1	472		T2	39		T3	80
valid_sources[0x43]	487000	1		T1	565		T2	30		T3	93
valid_sources[0x44]	487598	1		T1	561		T2	34		T3	81
valid_sources[0x45]	487905	1		T1	519		T2	51		T3	87
valid_sources[0x46]	485712	1		T1	481		T2	30		T3	53
valid_sources[0x47]	510902	1		T1	460		T2	32		T3	109
valid_sources[0x48]	488742	1		T1	518		T2	31		T3	87
valid_sources[0x49]	523765	1		T1	509		T2	24		T3	64
valid_sources[0x4a]	488924	1		T1	510		T2	47		T3	60
valid_sources[0x4b]	2779700	1		T1	469		T2	36		T3	81
valid_sources[0x4c]	485223	1		T1	569		T2	36		T3	62
valid_sources[0x4d]	500400	1		T1	632		T2	45		T3	65
valid_sources[0x4e]	489449	1		T1	500		T2	35		T3	90
valid_sources[0x4f]	491172	1		T1	511		T2	33		T3	88
valid_sources[0x50]	490399	1		T1	519		T2	27		T3	68
valid_sources[0x51]	490028	1		T1	545		T2	47		T3	113
valid_sources[0x52]	487632	1		T1	550		T2	37		T3	108
valid_sources[0x53]	526908	1		T1	585		T2	43		T3	72
valid_sources[0x54]	491150	1		T1	495		T2	37		T3	107
valid_sources[0x55]	583487	1		T1	504		T2	33		T3	59
valid_sources[0x56]	489779	1		T1	499		T2	34		T3	120
valid_sources[0x57]	490021	1		T1	528		T2	42		T3	94
valid_sources[0x58]	502602	1		T1	515		T2	29		T3	93
valid_sources[0x59]	537223	1		T1	494		T2	31		T3	115
valid_sources[0x5a]	488135	1		T1	491		T2	41		T3	120
valid_sources[0x5b]	491584	1		T1	501		T2	34		T3	87
valid_sources[0x5c]	529158	1		T1	549		T2	39		T3	77
valid_sources[0x5d]	490484	1		T1	470		T2	36		T3	138
valid_sources[0x5e]	489286	1		T1	506		T2	32		T3	96
valid_sources[0x5f]	723476	1		T1	481		T2	31		T3	110
valid_sources[0x60]	604126	1		T1	514		T2	39		T3	73
valid_sources[0x61]	1992247	1		T1	545		T2	37		T3	75
valid_sources[0x62]	487021	1		T1	500		T2	46		T3	85
valid_sources[0x63]	490882	1		T1	467		T2	30		T3	125
valid_sources[0x64]	985105	1		T1	485		T2	34		T3	78
valid_sources[0x65]	489488	1		T1	549		T2	30		T3	78
valid_sources[0x66]	485680	1		T1	602		T2	35		T3	99
valid_sources[0x67]	557608	1		T1	517		T2	44		T3	62
valid_sources[0x68]	486281	1		T1	467		T2	32		T3	96
valid_sources[0x69]	489185	1		T1	503		T2	31		T3	78
valid_sources[0x6a]	488274	1		T1	533		T2	23		T3	68
valid_sources[0x6b]	1007112	1		T1	609		T2	34		T3	85
valid_sources[0x6c]	490109	1		T1	512		T2	44		T3	76
valid_sources[0x6d]	486536	1		T1	545		T2	44		T3	91
valid_sources[0x6e]	489349	1		T1	549		T2	31		T3	98
valid_sources[0x6f]	487505	1		T1	510		T2	22		T3	79
valid_sources[0x70]	486062	1		T1	454		T2	28		T3	101
valid_sources[0x71]	485229	1		T1	560		T2	34		T3	62
valid_sources[0x72]	490879	1		T1	467		T2	35		T3	45
valid_sources[0x73]	540674	1		T1	503		T2	40		T3	91
valid_sources[0x74]	490476	1		T1	426		T2	28		T3	127
valid_sources[0x75]	779138	1		T1	484		T2	34		T3	131
valid_sources[0x76]	486984	1		T1	533		T2	36		T3	54
valid_sources[0x77]	485968	1		T1	517		T2	37		T3	72
valid_sources[0x78]	487801	1		T1	549		T2	24		T3	76
valid_sources[0x79]	929805	1		T1	468		T2	40		T3	100
valid_sources[0x7a]	489578	1		T1	591		T2	39		T3	90
valid_sources[0x7b]	493946	1		T1	553		T2	45		T3	73
valid_sources[0x7c]	487506	1		T1	548		T2	29		T3	93
valid_sources[0x7d]	517571	1		T1	540		T2	51		T3	99
valid_sources[0x7e]	709914	1		T1	528		T2	31		T3	61
valid_sources[0x7f]	524924	1		T1	559		T2	35		T3	50
valid_sources[0x80]	488644	1		T1	470		T2	38		T3	80

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72741833

1

T1

66434

T2

4566

T3

11193

values[0x0]

all_enables

biggest_size

48658

1

T1

53

T2

13

T3

13

values[0x1]

all_enables

biggest_size

47289

1

T1

55

T2

12

T3

4