Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	125204	0	0
cfg0_rd_A	2147483647	1310	0	0
compare_lower0_0_rd_A	2147483647	1174	0	0
compare_upper0_0_rd_A	2147483647	1073	0	0
ctrl_rd_A	2147483647	1121	0	0
intr_enable0_rd_A	2147483647	2080	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	125204	0	0
T13	176801	7247	0	0
T14	0	13386	0	0
T15	0	4031	0	0
T36	236848	0	0	0
T37	0	13834	0	0
T38	0	6038	0	0
T39	0	1644	0	0
T40	0	3196	0	0
T41	0	13196	0	0
T42	0	10055	0	0
T43	0	8663	0	0
T44	893391	0	0	0
T45	658444	0	0	0
T46	457996	0	0	0
T47	411945	0	0	0
T48	160788	0	0	0
T49	228705	0	0	0
T50	144895	0	0	0
T51	586139	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1310	0	0
T15	134506	52	0	0
T30	0	42	0	0
T34	0	216	0	0
T38	0	38	0	0
T40	0	80	0	0
T52	0	14	0	0
T53	0	7	0	0
T54	0	21	0	0
T55	0	30	0	0
T56	0	49	0	0
T57	640060	0	0	0
T58	134778	0	0	0
T59	831552	0	0	0
T60	165098	0	0	0
T61	108345	0	0	0
T62	864721	0	0	0
T63	147709	0	0	0
T64	736092	0	0	0
T65	115797	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1174	0	0
T15	134506	81	0	0
T30	0	12	0	0
T34	0	227	0	0
T38	0	44	0	0
T40	0	36	0	0
T52	0	11	0	0
T53	0	6	0	0
T54	0	11	0	0
T55	0	17	0	0
T56	0	80	0	0
T57	640060	0	0	0
T58	134778	0	0	0
T59	831552	0	0	0
T60	165098	0	0	0
T61	108345	0	0	0
T62	864721	0	0	0
T63	147709	0	0	0
T64	736092	0	0	0
T65	115797	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1073	0	0
T15	134506	46	0	0
T30	0	18	0	0
T34	0	216	0	0
T38	0	32	0	0
T40	0	40	0	0
T52	0	13	0	0
T53	0	10	0	0
T54	0	6	0	0
T55	0	13	0	0
T56	0	18	0	0
T57	640060	0	0	0
T58	134778	0	0	0
T59	831552	0	0	0
T60	165098	0	0	0
T61	108345	0	0	0
T62	864721	0	0	0
T63	147709	0	0	0
T64	736092	0	0	0
T65	115797	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1121	0	0
T15	134506	46	0	0
T30	0	37	0	0
T34	0	228	0	0
T38	0	39	0	0
T40	0	70	0	0
T52	0	13	0	0
T53	0	7	0	0
T54	0	12	0	0
T55	0	14	0	0
T57	640060	0	0	0
T58	134778	0	0	0
T59	831552	0	0	0
T60	165098	0	0	0
T61	108345	0	0	0
T62	864721	0	0	0
T63	147709	0	0	0
T64	736092	0	0	0
T65	115797	0	0	0
T66	0	5	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2080	0	0
T11	684224	25	0	0
T12	369607	0	0	0
T13	176801	0	0	0
T15	0	128	0	0
T22	0	22	0	0
T38	0	114	0	0
T40	0	95	0	0
T44	893391	0	0	0
T45	658444	0	0	0
T49	0	11	0	0
T67	0	64	0	0
T68	0	71	0	0
T69	0	47	0	0
T70	0	23	0	0
T71	212110	0	0	0
T72	692852	0	0	0
T73	133317	0	0	0
T74	621252	0	0	0
T75	342606	0	0	0