Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	166849	0	0
cfg0_rd_A	2147483647	1237	0	0
compare_lower0_0_rd_A	2147483647	1178	0	0
compare_upper0_0_rd_A	2147483647	1130	0	0
ctrl_rd_A	2147483647	1013	0	0
intr_enable0_rd_A	2147483647	2057	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	166849	0	0
T9	357492	10451	0	0
T10	132393	4364	0	0
T11	0	3963	0	0
T30	466474	0	0	0
T31	0	22963	0	0
T32	0	8098	0	0
T33	0	5777	0	0
T34	0	4390	0	0
T35	0	9579	0	0
T36	0	11300	0	0
T37	0	12862	0	0
T38	761488	0	0	0
T39	360169	0	0	0
T40	549561	0	0	0
T41	458293	0	0	0
T42	225228	0	0	0
T43	182396	0	0	0
T44	215183	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1237	0	0
T27	0	64	0	0
T28	0	7	0	0
T29	0	1	0	0
T34	154424	60	0	0
T45	0	105	0	0
T46	0	61	0	0
T47	0	1	0	0
T48	0	100	0	0
T49	0	17	0	0
T50	0	6	0	0
T51	280701	0	0	0
T52	414339	0	0	0
T53	516403	0	0	0
T54	118580	0	0	0
T55	418181	0	0	0
T56	937096	0	0	0
T57	440404	0	0	0
T58	180500	0	0	0
T59	3025	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1178	0	0
T27	0	45	0	0
T28	0	12	0	0
T29	0	1	0	0
T34	154424	81	0	0
T45	0	142	0	0
T46	0	45	0	0
T47	0	11	0	0
T48	0	62	0	0
T49	0	13	0	0
T50	0	7	0	0
T51	280701	0	0	0
T52	414339	0	0	0
T53	516403	0	0	0
T54	118580	0	0	0
T55	418181	0	0	0
T56	937096	0	0	0
T57	440404	0	0	0
T58	180500	0	0	0
T59	3025	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1130	0	0
T27	0	29	0	0
T28	0	2	0	0
T34	154424	54	0	0
T45	0	162	0	0
T46	0	46	0	0
T47	0	12	0	0
T48	0	72	0	0
T49	0	16	0	0
T50	0	5	0	0
T51	280701	0	0	0
T52	414339	0	0	0
T53	516403	0	0	0
T54	118580	0	0	0
T55	418181	0	0	0
T56	937096	0	0	0
T57	440404	0	0	0
T58	180500	0	0	0
T59	3025	0	0	0
T60	0	8	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1013	0	0
T27	0	32	0	0
T28	0	3	0	0
T34	154424	82	0	0
T45	0	104	0	0
T46	0	67	0	0
T47	0	11	0	0
T48	0	71	0	0
T49	0	10	0	0
T50	0	11	0	0
T51	280701	0	0	0
T52	414339	0	0	0
T53	516403	0	0	0
T54	118580	0	0	0
T55	418181	0	0	0
T56	937096	0	0	0
T57	440404	0	0	0
T58	180500	0	0	0
T59	3025	0	0	0
T60	0	3	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2057	0	0
T34	0	137	0	0
T42	225228	46	0	0
T43	182396	0	0	0
T44	215183	0	0	0
T59	0	40	0	0
T61	541546	72	0	0
T62	0	93	0	0
T63	0	48	0	0
T64	0	10	0	0
T65	0	38	0	0
T66	0	126	0	0
T67	0	29	0	0
T68	222537	0	0	0
T69	416052	0	0	0
T70	111538	0	0	0
T71	387223	0	0	0
T72	103934	0	0	0
T73	423091	0	0	0