Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65558773	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

65682822

1

T1

464868

T2

7349

T3

10932

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	131130865	1			T1	928628		T2	14839		T3	21616
values[0x0]	53554	1			T1	23		T2	14		T3	9
values[0x1]	57176	1			T1	34		T2	13		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52385701	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

78855894

1

T1

557787

T2

8817

T3

13086

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	400862	1			T2	52		T3	91		T4	438
valid_sources[0x01]	403758	1			T2	51		T3	72		T4	392
valid_sources[0x02]	401467	1			T2	70		T3	70		T4	362
valid_sources[0x03]	401386	1			T2	43		T3	76		T4	383
valid_sources[0x04]	1329193	1			T1	928685		T2	60		T3	83
valid_sources[0x05]	404793	1			T2	68		T3	89		T4	366
valid_sources[0x06]	404851	1			T2	77		T3	116		T4	364
valid_sources[0x07]	404512	1			T2	67		T3	95		T4	404
valid_sources[0x08]	405640	1			T2	67		T3	74		T4	373
valid_sources[0x09]	401520	1			T2	61		T3	72		T4	440
valid_sources[0x0a]	401162	1			T2	65		T3	95		T4	451
valid_sources[0x0b]	678888	1			T2	55		T3	91		T4	368
valid_sources[0x0c]	958519	1			T2	57		T3	94		T4	411
valid_sources[0x0d]	648589	1			T2	47		T3	70		T4	396
valid_sources[0x0e]	404194	1			T2	55		T3	117		T4	369
valid_sources[0x0f]	401042	1			T2	55		T3	105		T4	436
valid_sources[0x10]	401034	1			T2	48		T3	86		T4	336
valid_sources[0x11]	405789	1			T2	53		T3	86		T4	499
valid_sources[0x12]	403216	1			T2	62		T3	103		T4	407
valid_sources[0x13]	403880	1			T2	66		T3	56		T4	384
valid_sources[0x14]	405942	1			T2	44		T3	63		T4	392
valid_sources[0x15]	403566	1			T2	64		T3	88		T4	352
valid_sources[0x16]	401156	1			T2	66		T3	97		T4	397
valid_sources[0x17]	942846	1			T2	50		T3	103		T4	417
valid_sources[0x18]	403785	1			T2	65		T3	76		T4	452
valid_sources[0x19]	405441	1			T2	53		T3	100		T4	429
valid_sources[0x1a]	403649	1			T2	66		T3	78		T4	369
valid_sources[0x1b]	406269	1			T2	54		T3	78		T4	397
valid_sources[0x1c]	402812	1			T2	71		T3	69		T4	380
valid_sources[0x1d]	449988	1			T2	40		T3	83		T4	398
valid_sources[0x1e]	402701	1			T2	74		T3	63		T4	389
valid_sources[0x1f]	398440	1			T2	51		T3	106		T4	383
valid_sources[0x20]	403194	1			T2	57		T3	98		T4	374
valid_sources[0x21]	419618	1			T2	60		T3	94		T4	352
valid_sources[0x22]	402502	1			T2	57		T3	96		T4	323
valid_sources[0x23]	403363	1			T2	43		T3	99		T4	391
valid_sources[0x24]	1084967	1			T2	53		T3	78		T4	400
valid_sources[0x25]	401146	1			T2	56		T3	67		T4	390
valid_sources[0x26]	407678	1			T2	63		T3	79		T4	375
valid_sources[0x27]	399966	1			T2	63		T3	76		T4	372
valid_sources[0x28]	398001	1			T2	54		T3	82		T4	453
valid_sources[0x29]	405131	1			T2	45		T3	69		T4	386
valid_sources[0x2a]	402554	1			T2	60		T3	108		T4	422
valid_sources[0x2b]	398495	1			T2	49		T3	71		T4	360
valid_sources[0x2c]	401560	1			T2	58		T3	102		T4	412
valid_sources[0x2d]	423883	1			T2	57		T3	119		T4	377
valid_sources[0x2e]	400346	1			T2	64		T3	93		T4	357
valid_sources[0x2f]	398392	1			T2	61		T3	93		T4	381
valid_sources[0x30]	404725	1			T2	61		T3	54		T4	362
valid_sources[0x31]	406823	1			T2	64		T3	84		T4	386
valid_sources[0x32]	401844	1			T2	63		T3	75		T4	409
valid_sources[0x33]	402635	1			T2	48		T3	87		T4	429
valid_sources[0x34]	404636	1			T2	61		T3	86		T4	346
valid_sources[0x35]	1295604	1			T2	66		T3	87		T4	418
valid_sources[0x36]	400026	1			T2	55		T3	73		T4	369
valid_sources[0x37]	396185	1			T2	60		T3	56		T4	350
valid_sources[0x38]	405156	1			T2	56		T3	82		T4	413
valid_sources[0x39]	402431	1			T2	64		T3	67		T4	397
valid_sources[0x3a]	401403	1			T2	46		T3	74		T4	380
valid_sources[0x3b]	403820	1			T2	54		T3	42		T4	419
valid_sources[0x3c]	400945	1			T2	53		T3	74		T4	401
valid_sources[0x3d]	404174	1			T2	68		T3	98		T4	384
valid_sources[0x3e]	405635	1			T2	44		T3	83		T4	452
valid_sources[0x3f]	401450	1			T2	61		T3	80		T4	421
valid_sources[0x40]	401132	1			T2	69		T3	88		T4	352
valid_sources[0x41]	398428	1			T2	48		T3	95		T4	395
valid_sources[0x42]	403101	1			T2	57		T3	92		T4	434
valid_sources[0x43]	416466	1			T2	74		T3	95		T4	365
valid_sources[0x44]	402180	1			T2	82		T3	89		T4	393
valid_sources[0x45]	405977	1			T2	64		T3	79		T4	419
valid_sources[0x46]	402310	1			T2	61		T3	72		T4	445
valid_sources[0x47]	401344	1			T2	54		T3	97		T4	400
valid_sources[0x48]	464971	1			T2	68		T3	76		T4	386
valid_sources[0x49]	400748	1			T2	47		T3	98		T4	386
valid_sources[0x4a]	424328	1			T2	59		T3	76		T4	390
valid_sources[0x4b]	402731	1			T2	58		T3	48		T4	378
valid_sources[0x4c]	3099970	1			T2	67		T3	122		T4	424
valid_sources[0x4d]	645364	1			T2	70		T3	102		T4	440
valid_sources[0x4e]	402776	1			T2	62		T3	81		T4	346
valid_sources[0x4f]	401676	1			T2	59		T3	58		T4	367
valid_sources[0x50]	401773	1			T2	79		T3	105		T4	414
valid_sources[0x51]	620008	1			T2	65		T3	74		T4	346
valid_sources[0x52]	404092	1			T2	61		T3	119		T4	390
valid_sources[0x53]	403608	1			T2	60		T3	70		T4	387
valid_sources[0x54]	402688	1			T2	60		T3	107		T4	383
valid_sources[0x55]	405206	1			T2	59		T3	68		T4	375
valid_sources[0x56]	588449	1			T2	62		T3	84		T4	361
valid_sources[0x57]	401205	1			T2	55		T3	102		T4	372
valid_sources[0x58]	401831	1			T2	64		T3	106		T4	363
valid_sources[0x59]	401270	1			T2	62		T3	63		T4	397
valid_sources[0x5a]	406712	1			T2	59		T3	109		T4	383
valid_sources[0x5b]	794100	1			T2	45		T3	91		T4	415
valid_sources[0x5c]	402684	1			T2	62		T3	83		T4	431
valid_sources[0x5d]	626090	1			T2	61		T3	85		T4	394
valid_sources[0x5e]	402073	1			T2	71		T3	102		T4	396
valid_sources[0x5f]	402698	1			T2	53		T3	108		T4	442
valid_sources[0x60]	402444	1			T2	64		T3	64		T4	399
valid_sources[0x61]	1614514	1			T2	54		T3	86		T4	389
valid_sources[0x62]	402890	1			T2	42		T3	143		T4	375
valid_sources[0x63]	851211	1			T2	53		T3	90		T4	445
valid_sources[0x64]	2682231	1			T2	51		T3	95		T4	412
valid_sources[0x65]	630534	1			T2	55		T3	90		T4	362
valid_sources[0x66]	403731	1			T2	53		T3	92		T4	393
valid_sources[0x67]	401658	1			T2	59		T3	98		T4	365
valid_sources[0x68]	406664	1			T2	53		T3	80		T4	344
valid_sources[0x69]	404468	1			T2	56		T3	106		T4	413
valid_sources[0x6a]	402413	1			T2	57		T3	88		T4	420
valid_sources[0x6b]	403327	1			T2	72		T3	79		T4	352
valid_sources[0x6c]	401770	1			T2	56		T3	111		T4	411
valid_sources[0x6d]	405255	1			T2	71		T3	96		T4	426
valid_sources[0x6e]	462242	1			T2	52		T3	107		T4	403
valid_sources[0x6f]	404856	1			T2	48		T3	73		T4	377
valid_sources[0x70]	404327	1			T2	51		T3	86		T4	442
valid_sources[0x71]	2596827	1			T2	56		T3	78		T4	387
valid_sources[0x72]	403788	1			T2	60		T3	97		T4	392
valid_sources[0x73]	400217	1			T2	62		T3	75		T4	396
valid_sources[0x74]	401931	1			T2	48		T3	98		T4	424
valid_sources[0x75]	403672	1			T2	51		T3	72		T4	435
valid_sources[0x76]	401053	1			T2	55		T3	71		T4	357
valid_sources[0x77]	467415	1			T2	49		T3	92		T4	379
valid_sources[0x78]	403340	1			T2	58		T3	70		T4	454
valid_sources[0x79]	1543397	1			T2	66		T3	74		T4	455
valid_sources[0x7a]	402219	1			T2	57		T3	75		T4	400
valid_sources[0x7b]	457109	1			T2	65		T3	82		T4	414
valid_sources[0x7c]	399396	1			T2	77		T3	56		T4	337
valid_sources[0x7d]	483306	1			T2	53		T3	77		T4	368
valid_sources[0x7e]	431650	1			T2	54		T3	108		T4	440
valid_sources[0x7f]	427822	1			T2	65		T3	133		T4	378
valid_sources[0x80]	404330	1			T2	56		T3	74		T4	356

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65587912

1

T1

464830

T2

7326

T3

10909

values[0x0]

all_enables

biggest_size

48409

1

T1

18

T2

13

T3

9

values[0x1]

all_enables

biggest_size

46501

1

T1

20

T2

10

T3

14