Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	119683	0	0
cfg0_rd_A	2147483647	1135	0	0
compare_lower0_0_rd_A	2147483647	852	0	0
compare_upper0_0_rd_A	2147483647	1080	0	0
ctrl_rd_A	2147483647	972	0	0
intr_enable0_rd_A	2147483647	2005	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	119683	0	0
T12	266385	13148	0	0
T13	191093	8120	0	0
T14	0	3974	0	0
T36	0	2052	0	0
T37	0	10499	0	0
T38	0	4999	0	0
T39	0	2360	0	0
T40	0	6221	0	0
T41	0	8867	0	0
T42	0	3270	0	0
T43	269067	0	0	0
T44	471402	0	0	0
T45	640377	0	0	0
T46	437047	0	0	0
T47	197231	0	0	0
T48	913729	0	0	0
T49	859331	0	0	0
T50	815471	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1135	0	0
T32	0	4	0	0
T33	0	7	0	0
T37	351852	69	0	0
T42	0	39	0	0
T51	0	21	0	0
T52	0	41	0	0
T53	0	15	0	0
T54	0	5	0	0
T55	0	68	0	0
T56	0	16	0	0
T57	109469	0	0	0
T58	106537	0	0	0
T59	752790	0	0	0
T60	155778	0	0	0
T61	489301	0	0	0
T62	142122	0	0	0
T63	207805	0	0	0
T64	439334	0	0	0
T65	283246	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	852	0	0
T33	0	4	0	0
T37	351852	70	0	0
T42	0	39	0	0
T51	0	23	0	0
T52	0	8	0	0
T53	0	13	0	0
T54	0	15	0	0
T55	0	64	0	0
T57	109469	0	0	0
T58	106537	0	0	0
T59	752790	0	0	0
T60	155778	0	0	0
T61	489301	0	0	0
T62	142122	0	0	0
T63	207805	0	0	0
T64	439334	0	0	0
T65	283246	0	0	0
T66	0	4	0	0
T67	0	14	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1080	0	0
T32	0	3	0	0
T33	0	2	0	0
T37	351852	93	0	0
T42	0	73	0	0
T51	0	23	0	0
T52	0	67	0	0
T53	0	25	0	0
T54	0	7	0	0
T55	0	33	0	0
T57	109469	0	0	0
T58	106537	0	0	0
T59	752790	0	0	0
T60	155778	0	0	0
T61	489301	0	0	0
T62	142122	0	0	0
T63	207805	0	0	0
T64	439334	0	0	0
T65	283246	0	0	0
T66	0	39	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	972	0	0
T32	0	3	0	0
T37	351852	89	0	0
T42	0	60	0	0
T51	0	36	0	0
T52	0	15	0	0
T53	0	39	0	0
T54	0	13	0	0
T55	0	55	0	0
T57	109469	0	0	0
T58	106537	0	0	0
T59	752790	0	0	0
T60	155778	0	0	0
T61	489301	0	0	0
T62	142122	0	0	0
T63	207805	0	0	0
T64	439334	0	0	0
T65	283246	0	0	0
T66	0	20	0	0
T68	0	8	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2005	0	0
T5	380920	20	0	0
T6	356648	0	0	0
T7	243867	0	0	0
T8	209953	0	0	0
T9	809382	0	0	0
T10	218523	0	0	0
T11	197041	0	0	0
T24	0	32	0	0
T35	226789	0	0	0
T37	0	213	0	0
T42	0	242	0	0
T48	0	38	0	0
T51	0	90	0	0
T69	0	42	0	0
T70	0	41	0	0
T71	0	17	0	0
T72	0	10	0	0
T73	128952	0	0	0
T74	192289	0	0	0