Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	183345	0	0
cfg0_rd_A	2147483647	1620	0	0
compare_lower0_0_rd_A	2147483647	1382	0	0
compare_upper0_0_rd_A	2147483647	1336	0	0
ctrl_rd_A	2147483647	1358	0	0
intr_enable0_rd_A	2147483647	2209	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	183345	0	0
T13	481235	21349	0	0
T14	385270	10202	0	0
T15	0	11155	0	0
T29	0	13370	0	0
T30	0	14178	0	0
T31	0	15979	0	0
T32	0	3765	0	0
T33	0	9161	0	0
T34	0	2840	0	0
T35	0	6984	0	0
T36	646221	0	0	0
T37	3381	0	0	0
T38	283349	0	0	0
T39	706581	0	0	0
T40	126448	0	0	0
T41	444519	0	0	0
T42	320270	0	0	0
T43	189777	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1620	0	0
T14	385270	150	0	0
T24	0	33	0	0
T26	0	20	0	0
T28	0	3	0	0
T32	0	38	0	0
T37	3381	0	0	0
T38	283349	0	0	0
T39	706581	0	0	0
T40	126448	0	0	0
T41	444519	0	0	0
T42	320270	0	0	0
T43	189777	0	0	0
T44	0	65	0	0
T45	0	6	0	0
T46	0	16	0	0
T47	0	18	0	0
T48	0	17	0	0
T49	489064	0	0	0
T50	154561	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1382	0	0
T14	385270	154	0	0
T24	0	48	0	0
T26	0	15	0	0
T28	0	9	0	0
T32	0	68	0	0
T37	3381	0	0	0
T38	283349	0	0	0
T39	706581	0	0	0
T40	126448	0	0	0
T41	444519	0	0	0
T42	320270	0	0	0
T43	189777	0	0	0
T44	0	66	0	0
T45	0	14	0	0
T46	0	3	0	0
T47	0	12	0	0
T49	489064	0	0	0
T50	154561	0	0	0
T51	0	12	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1336	0	0
T14	385270	148	0	0
T24	0	42	0	0
T26	0	18	0	0
T28	0	10	0	0
T32	0	46	0	0
T37	3381	0	0	0
T38	283349	0	0	0
T39	706581	0	0	0
T40	126448	0	0	0
T41	444519	0	0	0
T42	320270	0	0	0
T43	189777	0	0	0
T44	0	62	0	0
T45	0	11	0	0
T46	0	10	0	0
T47	0	6	0	0
T49	489064	0	0	0
T50	154561	0	0	0
T51	0	11	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1358	0	0
T14	385270	153	0	0
T24	0	44	0	0
T26	0	9	0	0
T28	0	5	0	0
T32	0	43	0	0
T37	3381	0	0	0
T38	283349	0	0	0
T39	706581	0	0	0
T40	126448	0	0	0
T41	444519	0	0	0
T42	320270	0	0	0
T43	189777	0	0	0
T44	0	63	0	0
T45	0	9	0	0
T46	0	8	0	0
T47	0	9	0	0
T49	489064	0	0	0
T50	154561	0	0	0
T51	0	6	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2209	0	0
T5	430923	10	0	0
T6	5855	0	0	0
T7	231534	0	0	0
T8	312301	0	0	0
T9	375988	0	0	0
T10	127228	0	0	0
T11	687651	0	0	0
T12	654494	0	0	0
T14	0	160	0	0
T20	100853	0	0	0
T21	266414	0	0	0
T32	0	74	0	0
T52	0	21	0	0
T53	0	127	0	0
T54	0	58	0	0
T55	0	16	0	0
T56	0	51	0	0
T57	0	88	0	0
T58	0	72	0	0