Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	72061229	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

72204627

1

T1

1099

T2

364352

T3

29501

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	144136859	1			T1	2190		T2	727712		T3	58648
values[0x0]	61997	1			T1	2		T2	87		T3	22
values[0x1]	67000	1			T1	8		T2	102		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57586271	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

86679585

1

T1

1317

T2

437199

T3

35346

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	432311	1			T1	5		T4	51		T6	3608
valid_sources[0x01]	433373	1			T1	12		T4	61		T6	3527
valid_sources[0x02]	432421	1			T1	10		T4	66		T6	3563
valid_sources[0x03]	432007	1			T1	7		T4	47		T6	3440
valid_sources[0x04]	431646	1			T1	3		T4	45		T6	3621
valid_sources[0x05]	1021754	1			T1	4		T4	68		T6	3677
valid_sources[0x06]	433327	1			T1	16		T4	45		T6	3475
valid_sources[0x07]	439188	1			T1	13		T4	56		T6	3567
valid_sources[0x08]	433345	1			T1	6		T4	48		T6	3486
valid_sources[0x09]	433351	1			T1	13		T4	50		T6	3615
valid_sources[0x0a]	487846	1			T1	10		T4	44		T6	3579
valid_sources[0x0b]	436074	1			T1	10		T4	51		T6	3664
valid_sources[0x0c]	429580	1			T1	7		T4	45		T6	3505
valid_sources[0x0d]	434432	1			T1	7		T4	41		T6	3585
valid_sources[0x0e]	434949	1			T1	8		T4	58		T6	3640
valid_sources[0x0f]	443188	1			T1	5		T4	53		T6	3609
valid_sources[0x10]	489608	1			T1	12		T3	58689		T4	51
valid_sources[0x11]	433504	1			T1	10		T4	51		T6	3710
valid_sources[0x12]	451432	1			T1	9		T4	58		T6	3532
valid_sources[0x13]	430990	1			T1	10		T4	43		T6	3444
valid_sources[0x14]	459794	1			T1	5		T4	45		T6	3571
valid_sources[0x15]	431088	1			T1	15		T4	38		T6	3677
valid_sources[0x16]	432503	1			T1	9		T4	43		T6	3756
valid_sources[0x17]	432935	1			T1	12		T4	48		T6	3622
valid_sources[0x18]	1965754	1			T1	8		T4	47		T6	3479
valid_sources[0x19]	433944	1			T1	8		T4	46		T6	3608
valid_sources[0x1a]	444728	1			T1	10		T4	45		T6	3513
valid_sources[0x1b]	774905	1			T1	5		T4	48		T6	3646
valid_sources[0x1c]	433663	1			T1	12		T4	45		T6	3717
valid_sources[0x1d]	432107	1			T1	4		T4	45		T6	3616
valid_sources[0x1e]	432363	1			T1	8		T4	37		T6	3497
valid_sources[0x1f]	845582	1			T1	6		T4	49		T6	3381
valid_sources[0x20]	428633	1			T1	10		T4	60		T6	3706
valid_sources[0x21]	606640	1			T1	9		T4	49		T6	3621
valid_sources[0x22]	431523	1			T1	12		T4	49		T6	3500
valid_sources[0x23]	504639	1			T1	15		T4	52		T6	3737
valid_sources[0x24]	430778	1			T1	9		T4	42		T6	3542
valid_sources[0x25]	772733	1			T1	7		T4	57		T6	3607
valid_sources[0x26]	432586	1			T1	6		T4	55		T6	3479
valid_sources[0x27]	432889	1			T1	12		T4	52		T6	3772
valid_sources[0x28]	434356	1			T1	12		T4	56		T6	3520
valid_sources[0x29]	431129	1			T1	6		T4	56		T6	3572
valid_sources[0x2a]	429997	1			T1	3		T4	36		T6	3583
valid_sources[0x2b]	508747	1			T1	15		T4	32		T6	3474
valid_sources[0x2c]	582519	1			T1	13		T4	41		T6	3636
valid_sources[0x2d]	437433	1			T1	18		T4	44		T6	3584
valid_sources[0x2e]	1734822	1			T1	8		T4	45		T6	3436
valid_sources[0x2f]	432694	1			T1	9		T4	50		T6	3634
valid_sources[0x30]	433593	1			T1	11		T4	46		T6	3562
valid_sources[0x31]	433421	1			T1	4		T4	40		T6	3601
valid_sources[0x32]	432762	1			T1	4		T4	44		T6	3697
valid_sources[0x33]	431923	1			T1	10		T4	45		T6	3565
valid_sources[0x34]	432263	1			T1	7		T4	53		T6	3599
valid_sources[0x35]	433527	1			T1	4		T4	46		T6	3680
valid_sources[0x36]	432375	1			T1	4		T4	43		T6	3493
valid_sources[0x37]	433792	1			T1	7		T4	43		T6	3386
valid_sources[0x38]	433581	1			T1	8		T4	47		T6	3486
valid_sources[0x39]	432464	1			T1	9		T4	60		T6	3589
valid_sources[0x3a]	431916	1			T1	8		T4	65		T6	3633
valid_sources[0x3b]	466871	1			T1	7		T4	58		T6	3510
valid_sources[0x3c]	493305	1			T1	6		T4	50		T6	3595
valid_sources[0x3d]	487476	1			T1	12		T4	44		T6	3862
valid_sources[0x3e]	435637	1			T1	10		T4	57		T6	3531
valid_sources[0x3f]	430379	1			T1	12		T4	58		T6	3544
valid_sources[0x40]	431940	1			T1	9		T4	50		T6	3513
valid_sources[0x41]	432577	1			T1	11		T4	51		T6	3505
valid_sources[0x42]	431021	1			T1	17		T4	47		T6	3562
valid_sources[0x43]	436373	1			T1	12		T4	44		T6	3481
valid_sources[0x44]	433131	1			T1	5		T4	50		T6	3744
valid_sources[0x45]	434072	1			T1	13		T4	53		T6	3546
valid_sources[0x46]	435717	1			T1	7		T4	48		T6	3626
valid_sources[0x47]	430967	1			T1	11		T4	54		T6	3629
valid_sources[0x48]	433103	1			T1	3		T4	31		T6	3608
valid_sources[0x49]	432398	1			T1	11		T4	59		T6	3601
valid_sources[0x4a]	434659	1			T1	9		T4	45		T6	3590
valid_sources[0x4b]	431215	1			T1	5		T4	61		T6	3469
valid_sources[0x4c]	432602	1			T1	12		T4	54		T6	3757
valid_sources[0x4d]	431275	1			T1	8		T4	46		T6	3723
valid_sources[0x4e]	432770	1			T1	9		T4	38		T6	3283
valid_sources[0x4f]	472734	1			T1	10		T4	55		T6	3587
valid_sources[0x50]	429888	1			T1	7		T4	55		T6	3575
valid_sources[0x51]	428099	1			T1	6		T4	48		T6	3443
valid_sources[0x52]	465290	1			T1	8		T4	49		T6	3797
valid_sources[0x53]	433138	1			T1	8		T4	46		T6	3580
valid_sources[0x54]	431534	1			T1	9		T4	38		T6	3665
valid_sources[0x55]	433712	1			T1	3		T4	53		T6	3568
valid_sources[0x56]	435209	1			T1	4		T4	44		T6	3484
valid_sources[0x57]	515094	1			T1	6		T4	48		T6	3682
valid_sources[0x58]	432240	1			T1	11		T4	59		T6	3510
valid_sources[0x59]	1263557	1			T1	10		T4	53		T6	3521
valid_sources[0x5a]	436507	1			T1	9		T4	41		T6	3610
valid_sources[0x5b]	430551	1			T1	12		T4	60		T6	3576
valid_sources[0x5c]	1016868	1			T1	9		T4	39		T6	3450
valid_sources[0x5d]	435977	1			T1	5		T4	46		T6	3479
valid_sources[0x5e]	435116	1			T1	7		T4	55		T6	3606
valid_sources[0x5f]	429562	1			T1	4		T4	53		T6	3668
valid_sources[0x60]	434891	1			T1	9		T4	44		T6	3615
valid_sources[0x61]	428865	1			T1	10		T4	41		T6	3534
valid_sources[0x62]	1025837	1			T1	10		T4	72		T6	3593
valid_sources[0x63]	431873	1			T1	6		T4	53		T6	3430
valid_sources[0x64]	433729	1			T1	7		T4	50		T6	3541
valid_sources[0x65]	431948	1			T1	6		T4	70		T6	3587
valid_sources[0x66]	433906	1			T1	8		T4	57		T6	3482
valid_sources[0x67]	433614	1			T1	11		T4	44		T6	3517
valid_sources[0x68]	686189	1			T1	10		T4	42		T6	3458
valid_sources[0x69]	436048	1			T1	11		T4	51		T6	3639
valid_sources[0x6a]	497455	1			T1	9		T4	47		T6	3539
valid_sources[0x6b]	433263	1			T1	8		T4	40		T6	3496
valid_sources[0x6c]	866685	1			T1	10		T4	48		T6	3507
valid_sources[0x6d]	433400	1			T1	12		T4	51		T6	3611
valid_sources[0x6e]	434085	1			T1	8		T4	50		T6	3702
valid_sources[0x6f]	433975	1			T1	9		T4	62		T5	581
valid_sources[0x70]	431170	1			T1	3		T4	48		T6	3566
valid_sources[0x71]	436460	1			T1	5		T4	56		T6	3682
valid_sources[0x72]	1779968	1			T1	3		T4	48		T6	3591
valid_sources[0x73]	430829	1			T1	4		T4	48		T6	3765
valid_sources[0x74]	432646	1			T1	11		T4	55		T6	3676
valid_sources[0x75]	843798	1			T1	5		T4	59		T6	3730
valid_sources[0x76]	435373	1			T1	6		T4	56		T6	3624
valid_sources[0x77]	430803	1			T1	15		T4	58		T6	3624
valid_sources[0x78]	437646	1			T1	10		T4	36		T6	3543
valid_sources[0x79]	438976	1			T1	4		T4	53		T6	3777
valid_sources[0x7a]	434729	1			T1	4		T4	62		T6	3592
valid_sources[0x7b]	432812	1			T1	4		T4	36		T6	3565
valid_sources[0x7c]	444716	1			T1	6		T4	63		T6	3524
valid_sources[0x7d]	436051	1			T1	5		T4	48		T6	3648
valid_sources[0x7e]	432981	1			T1	6		T4	54		T6	3600
valid_sources[0x7f]	435164	1			T1	13		T4	56		T6	3551
valid_sources[0x80]	672467	1			T1	6		T4	50		T6	3752

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72091952

1

T1

1093

T2

364256

T3

29473

values[0x0]

all_enables

biggest_size

57037

1

T1

2

T2

45

T3

14

values[0x1]

all_enables

biggest_size

55638

1

T1

4

T2

51

T3

14