Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	149900	0	0
cfg0_rd_A	2147483647	1130	0	0
compare_lower0_0_rd_A	2147483647	1092	0	0
compare_upper0_0_rd_A	2147483647	968	0	0
ctrl_rd_A	2147483647	1063	0	0
intr_enable0_rd_A	2147483647	2019	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	149900	0	0
T4	543338	14081	0	0
T5	119423	0	0	0
T6	629918	0	0	0
T7	148533	0	0	0
T8	679591	0	0	0
T9	136216	0	0	0
T10	103872	0	0	0
T11	0	4478	0	0
T12	0	9800	0	0
T33	0	5859	0	0
T34	0	12982	0	0
T35	0	5019	0	0
T36	0	3592	0	0
T37	0	14995	0	0
T38	0	6141	0	0
T39	0	6166	0	0
T40	308871	0	0	0
T41	169862	0	0	0
T42	193192	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1130	0	0
T4	543338	170	0	0
T5	119423	0	0	0
T6	629918	0	0	0
T7	148533	0	0	0
T8	679591	0	0	0
T9	136216	0	0	0
T10	103872	0	0	0
T11	0	73	0	0
T40	308871	0	0	0
T41	169862	0	0	0
T42	193192	0	0	0
T43	0	164	0	0
T44	0	48	0	0
T45	0	30	0	0
T46	0	4	0	0
T47	0	8	0	0
T48	0	7	0	0
T49	0	15	0	0
T50	0	112	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1092	0	0
T4	543338	218	0	0
T5	119423	0	0	0
T6	629918	0	0	0
T7	148533	0	0	0
T8	679591	0	0	0
T9	136216	0	0	0
T10	103872	0	0	0
T11	0	102	0	0
T40	308871	0	0	0
T41	169862	0	0	0
T42	193192	0	0	0
T43	0	97	0	0
T44	0	36	0	0
T45	0	47	0	0
T46	0	4	0	0
T47	0	3	0	0
T48	0	9	0	0
T49	0	6	0	0
T50	0	87	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	968	0	0
T4	543338	98	0	0
T5	119423	0	0	0
T6	629918	0	0	0
T7	148533	0	0	0
T8	679591	0	0	0
T9	136216	0	0	0
T10	103872	0	0	0
T11	0	62	0	0
T40	308871	0	0	0
T41	169862	0	0	0
T42	193192	0	0	0
T43	0	108	0	0
T44	0	45	0	0
T45	0	65	0	0
T48	0	7	0	0
T49	0	6	0	0
T50	0	88	0	0
T51	0	54	0	0
T52	0	2	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1063	0	0
T4	543338	203	0	0
T5	119423	0	0	0
T6	629918	0	0	0
T7	148533	0	0	0
T8	679591	0	0	0
T9	136216	0	0	0
T10	103872	0	0	0
T11	0	43	0	0
T40	308871	0	0	0
T41	169862	0	0	0
T42	193192	0	0	0
T43	0	99	0	0
T44	0	58	0	0
T45	0	28	0	0
T46	0	3	0	0
T47	0	10	0	0
T48	0	10	0	0
T49	0	5	0	0
T50	0	88	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2019	0	0
T4	543338	385	0	0
T5	119423	0	0	0
T6	629918	0	0	0
T7	148533	0	0	0
T8	679591	0	0	0
T9	136216	0	0	0
T10	103872	0	0	0
T11	0	93	0	0
T40	308871	0	0	0
T41	169862	0	0	0
T42	193192	0	0	0
T53	0	58	0	0
T54	0	39	0	0
T55	0	79	0	0
T56	0	43	0	0
T57	0	114	0	0
T58	0	9	0	0
T59	0	21	0	0
T60	0	43	0	0