Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62091950	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

62204710

1

T2

1

T3

38

T4

9314

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	124170526	1			T1	1		T2	1		T3	58
values[0x0]	60596	1			T3	32		T4	17		T6	14
values[0x1]	65538	1			T3	25		T4	23		T6	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49616776	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

74679884

1

T2

1

T3

49

T4

11148

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	373542	1			T10	1		T11	15		T20	17
valid_sources[0x01]	389463	1			T11	9		T20	21		T14	20
valid_sources[0x02]	373291	1			T6	24		T10	52		T11	15
valid_sources[0x03]	370145	1			T10	1		T11	13		T20	24
valid_sources[0x04]	371105	1			T10	1		T11	8		T20	19
valid_sources[0x05]	370823	1			T3	4		T10	80		T11	12
valid_sources[0x06]	368829	1			T10	19		T11	6		T20	13
valid_sources[0x07]	372139	1			T1	1		T10	27		T11	7
valid_sources[0x08]	917645	1			T3	4		T10	1		T11	25
valid_sources[0x09]	372025	1			T11	21		T20	16		T14	14
valid_sources[0x0a]	370897	1			T10	1		T11	17		T20	22
valid_sources[0x0b]	444999	1			T10	34		T11	11		T20	16
valid_sources[0x0c]	369734	1			T10	1		T11	8		T20	31
valid_sources[0x0d]	645290	1			T11	6		T20	17		T14	24
valid_sources[0x0e]	497073	1			T6	22		T11	36		T20	19
valid_sources[0x0f]	372482	1			T11	7		T20	14		T14	18
valid_sources[0x10]	370316	1			T10	93		T11	17		T20	26
valid_sources[0x11]	369967	1			T10	26		T11	6		T20	18
valid_sources[0x12]	371122	1			T3	2		T10	1		T11	11
valid_sources[0x13]	916215	1			T10	3		T11	12		T20	19
valid_sources[0x14]	370111	1			T10	37		T11	11		T20	19
valid_sources[0x15]	370384	1			T10	49		T11	1		T20	17
valid_sources[0x16]	374256	1			T10	3		T11	18		T20	19
valid_sources[0x17]	1529122	1			T10	53		T11	31		T20	28
valid_sources[0x18]	426086	1			T10	23		T11	46		T20	20
valid_sources[0x19]	525328	1			T10	14		T11	17		T20	23
valid_sources[0x1a]	371784	1			T10	17		T11	15		T20	16
valid_sources[0x1b]	369851	1			T10	2		T11	31		T20	18
valid_sources[0x1c]	369077	1			T10	1		T11	7		T20	24
valid_sources[0x1d]	369078	1			T3	2		T10	62		T11	9
valid_sources[0x1e]	368285	1			T10	4		T11	4		T20	16
valid_sources[0x1f]	374092	1			T10	8		T11	11		T20	15
valid_sources[0x20]	449104	1			T10	3		T11	9		T20	21
valid_sources[0x21]	369621	1			T10	89		T11	9		T20	18
valid_sources[0x22]	371429	1			T11	13		T20	21		T14	20
valid_sources[0x23]	370992	1			T11	8		T20	19		T14	13
valid_sources[0x24]	371210	1			T10	41		T11	27		T20	24
valid_sources[0x25]	383332	1			T10	1		T11	8		T20	20
valid_sources[0x26]	367954	1			T10	1		T11	19		T20	17
valid_sources[0x27]	376928	1			T6	1		T11	15		T20	21
valid_sources[0x28]	373150	1			T10	25		T11	28		T20	28
valid_sources[0x29]	370179	1			T3	2		T6	43		T10	2
valid_sources[0x2a]	370818	1			T10	73		T11	27		T20	27
valid_sources[0x2b]	371988	1			T10	14		T11	17		T20	14
valid_sources[0x2c]	1329450	1			T6	22		T10	17		T11	17
valid_sources[0x2d]	369687	1			T3	4		T10	9		T11	22
valid_sources[0x2e]	367751	1			T10	5		T11	4		T20	34
valid_sources[0x2f]	372033	1			T3	1		T11	34		T20	23
valid_sources[0x30]	369529	1			T10	50		T11	15		T20	24
valid_sources[0x31]	370520	1			T10	2		T11	37		T20	24
valid_sources[0x32]	370197	1			T10	4		T11	25		T20	33
valid_sources[0x33]	2249462	1			T10	11		T11	25		T20	19
valid_sources[0x34]	369860	1			T3	1		T11	2		T20	29
valid_sources[0x35]	371838	1			T10	2		T11	9		T20	16
valid_sources[0x36]	379251	1			T3	1		T6	29		T11	10
valid_sources[0x37]	453373	1			T11	8		T20	21		T14	18
valid_sources[0x38]	373894	1			T6	4		T10	6		T11	16
valid_sources[0x39]	373235	1			T10	42		T11	26		T20	13
valid_sources[0x3a]	371012	1			T11	13		T20	6		T14	13
valid_sources[0x3b]	375627	1			T6	9		T11	20		T20	14
valid_sources[0x3c]	371896	1			T7	1		T10	70		T11	15
valid_sources[0x3d]	374058	1			T10	27		T11	19		T20	19
valid_sources[0x3e]	373355	1			T10	2		T11	10		T20	21
valid_sources[0x3f]	375682	1			T10	129		T11	11		T20	16
valid_sources[0x40]	902238	1			T11	26		T20	20		T14	21
valid_sources[0x41]	368591	1			T11	13		T20	24		T14	20
valid_sources[0x42]	375831	1			T6	20		T10	74		T11	24
valid_sources[0x43]	371480	1			T11	13		T20	17		T14	10
valid_sources[0x44]	371074	1			T10	2		T11	18		T20	15
valid_sources[0x45]	368486	1			T5	1		T10	17		T11	8
valid_sources[0x46]	369107	1			T11	27		T20	18		T14	13
valid_sources[0x47]	370705	1			T3	2		T10	5		T11	3
valid_sources[0x48]	372515	1			T11	21		T20	16		T14	19
valid_sources[0x49]	373739	1			T6	2		T10	1		T11	30
valid_sources[0x4a]	373910	1			T10	1		T11	38		T20	24
valid_sources[0x4b]	368528	1			T10	23		T11	14		T20	17
valid_sources[0x4c]	371354	1			T10	1		T11	14		T20	16
valid_sources[0x4d]	371295	1			T10	52		T11	12		T20	11
valid_sources[0x4e]	374016	1			T3	1		T10	24		T11	22
valid_sources[0x4f]	373564	1			T10	41		T11	17		T20	19
valid_sources[0x50]	378913	1			T10	18		T11	9		T20	20
valid_sources[0x51]	369219	1			T10	112		T11	13		T20	21
valid_sources[0x52]	371319	1			T11	9		T20	22		T14	18
valid_sources[0x53]	378103	1			T6	20		T11	36		T20	20
valid_sources[0x54]	372576	1			T10	2		T11	19		T20	16
valid_sources[0x55]	371953	1			T10	2		T11	13		T20	21
valid_sources[0x56]	371910	1			T10	2		T11	11		T20	21
valid_sources[0x57]	370650	1			T6	52		T10	13		T11	6
valid_sources[0x58]	369069	1			T6	31		T10	53		T11	12
valid_sources[0x59]	366884	1			T10	73		T11	11		T20	17
valid_sources[0x5a]	575924	1			T10	26		T11	30		T20	17
valid_sources[0x5b]	1145591	1			T10	10		T11	23		T20	19
valid_sources[0x5c]	394375	1			T10	60		T11	22		T20	23
valid_sources[0x5d]	367391	1			T10	37		T11	15		T20	21
valid_sources[0x5e]	371271	1			T6	6		T11	8		T20	19
valid_sources[0x5f]	369785	1			T8	1		T10	1		T11	51
valid_sources[0x60]	418058	1			T3	3		T11	14		T20	19
valid_sources[0x61]	721040	1			T10	1		T11	7		T20	23
valid_sources[0x62]	370544	1			T10	1		T11	34		T20	16
valid_sources[0x63]	372372	1			T10	72		T11	18		T20	22
valid_sources[0x64]	370263	1			T3	3		T10	1		T11	52
valid_sources[0x65]	3034275	1			T11	15		T20	21		T14	12
valid_sources[0x66]	371170	1			T10	122		T11	19		T20	15
valid_sources[0x67]	370763	1			T3	4		T11	6		T20	13
valid_sources[0x68]	1209282	1			T11	18		T20	18		T14	12
valid_sources[0x69]	431179	1			T11	15		T20	26		T14	20
valid_sources[0x6a]	372714	1			T10	3		T11	19		T20	15
valid_sources[0x6b]	372261	1			T6	22		T11	2		T20	23
valid_sources[0x6c]	372770	1			T10	96		T11	4		T20	27
valid_sources[0x6d]	367661	1			T10	88		T11	24		T20	21
valid_sources[0x6e]	371601	1			T10	2		T11	16		T20	23
valid_sources[0x6f]	373313	1			T10	3		T11	5		T20	25
valid_sources[0x70]	371052	1			T6	25		T11	13		T20	13
valid_sources[0x71]	370431	1			T10	2		T11	22		T20	25
valid_sources[0x72]	400464	1			T3	7		T10	12		T11	54
valid_sources[0x73]	375002	1			T10	4		T11	8		T20	22
valid_sources[0x74]	389055	1			T10	16		T11	14		T20	23
valid_sources[0x75]	453067	1			T6	27		T10	3		T11	40
valid_sources[0x76]	370211	1			T3	12		T10	2		T11	13
valid_sources[0x77]	400152	1			T11	26		T20	18		T14	9
valid_sources[0x78]	370828	1			T11	15		T20	23		T14	10
valid_sources[0x79]	435456	1			T10	53		T11	18		T20	21
valid_sources[0x7a]	371295	1			T6	7		T10	1		T11	36
valid_sources[0x7b]	366422	1			T3	7		T10	11		T11	10
valid_sources[0x7c]	370317	1			T2	1		T10	65		T11	19
valid_sources[0x7d]	754692	1			T10	7		T11	14		T20	16
valid_sources[0x7e]	414795	1			T11	15		T20	15		T14	14
valid_sources[0x7f]	371186	1			T10	1		T11	17		T20	17
valid_sources[0x80]	372650	1			T10	15		T11	21		T20	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62095078

1

T2

1

T3

26

T4

9285

values[0x0]

all_enables

biggest_size

55422

1

T3

6

T4

14

T6

10

values[0x1]

all_enables

biggest_size

54210

1

T3

6

T4

15

T6

6