Unified Coverage Report :: Group :: dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg

Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv

19 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rv_timer-0-prescale-0	100.00	1	100	1	64	64
rv_timer-0-prescale-1	100.00	1	100	1	64	64
rv_timer-0-prescale-10	100.00	1	100	1	64	64
rv_timer-0-prescale-11	100.00	1	100	1	64	64
rv_timer-0-prescale-2	100.00	1	100	1	64	64
rv_timer-0-prescale-3	100.00	1	100	1	64	64
rv_timer-0-prescale-4	100.00	1	100	1	64	64
rv_timer-0-prescale-5	100.00	1	100	1	64	64
rv_timer-0-prescale-6	100.00	1	100	1	64	64
rv_timer-0-prescale-7	100.00	1	100	1	64	64
rv_timer-0-prescale-8	100.00	1	100	1	64	64
rv_timer-0-prescale-9	100.00	1	100	1	64	64
rv_timer_sticky_intr_pin0	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max	100.00	1	100	1	64	64

---

Group Instance : rv_timer-0-prescale-0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-10

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-10

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-10

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-11

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-11

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-11

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-6

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-6

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-6

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-7

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-7

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-7

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-8

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-8

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-8

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-9

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-9

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-9

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer_sticky_intr_pin0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer_sticky_intr_pin0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer_sticky_intr_pin0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

213

1

T4

1

T99

1

T135

1

rising

228

1

T4

1

T12

1

T13

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

588

1

T4

1

T12

1

T29

1

auto[1]

579

1

T4

3

T12

2

T30

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

201

1

T83

1

T101

1

T131

1

rising

205

1

T98

1

T83

1

T99

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

559

1

T4

4

T30

1

T37

1

auto[1]

608

1

T12

3

T29

1

T98

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

221

1

T4

1

T13

1

T98

1

rising

192

1

T4

1

T12

1

T99

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

621

1

T4

3

T12

1

T37

1

auto[1]

546

1

T4

1

T12

2

T29

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

213

1

T4

1

T13

1

T83

1

rising

218

1

T12

1

T98

1

T83

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

604

1

T4

2

T12

2

T30

1

auto[1]

563

1

T4

2

T12

1

T29

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

224

1

T12

1

T98

1

T83

1

rising

215

1

T4

1

T13

1

T124

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

576

1

T4

2

T12

2

T37

1

auto[1]

591

1

T4

2

T12

1

T29

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

203

1

T4

1

T83

1

T135

1

rising

225

1

T4

1

T12

1

T83

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

607

1

T4

2

T12

1

T102

1

auto[1]

560

1

T4

2

T12

2

T29

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

203

1

T4

1

T12

1

T99

1

rising

219

1

T4

1

T12

1

T135

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

593

1

T4

3

T12

1

T30

1

auto[1]

574

1

T4

1

T12

2

T29

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

223

1

T4

1

T12

1

T83

1

rising

209

1

T4

1

T12

1

T98

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

586

1

T4

1

T12

1

T30

1

auto[1]

581

1

T4

3

T12

2

T29

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

209

1

T4

1

T13

1

T83

1

rising

209

1

T12

1

T98

1

T83

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

609

1

T4

1

T12

1

T29

1

auto[1]

558

1

T4

3

T12

2

T30

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

208

1

T4

1

T98

1

T83

2

rising

204

1

T12

1

T13

1

T83

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

597

1

T4

2

T12

1

T30

1

auto[1]

570

1

T4

2

T12

2

T29

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

207

1

T4

2

T99

1

T86

1

rising

222

1

T4

1

T13

1

T83

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

573

1

T4

2

T29

1

T30

1

auto[1]

594

1

T4

2

T12

3

T13

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

206

1

T4

1

T12

1

T13

1

rising

212

1

T90

1

T137

1

T70

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

561

1

T4

1

T12

2

T37

1

auto[1]

606

1

T4

3

T12

1

T29

1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

66

1

T12

2

T13

1

T98

1

rising

66

1

T12

2

T13

1

T98

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6871

1

T3

14

T4

14

T6

8

auto[1]

106

1

T12

3

T13

2

T98

2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

26208

1

T10

1247

T11

886

T14

597

rising

26212

1

T10

1247

T11

886

T14

597

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178425

1

T10

8370

T11

6288

T14

3858

auto[1]

31409

1

T10

1492

T11

1060

T14

729

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

50099

1

T10

2374

T11

1713

T14

1051

rising

50106

1

T10

2374

T11

1712

T14

1052

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124695

1

T10

5798

T11

4375

T14

2808

auto[1]

85139

1

T10

4064

T11

2973

T14

1779

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

50099

1

T10

2374

T11

1713

T14

1051

rising

50106

1

T10

2374

T11

1712

T14

1052

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124695

1

T10

5798

T11

4375

T14

2808

auto[1]

85139

1

T10

4064

T11

2973

T14

1779

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

51403

1

T10

2419

T11

1823

T14

1119

rising

51404

1

T10

2419

T11

1823

T14

1120

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113114

1

T10

5260

T11

3926

T14

2587

auto[1]

96720

1

T10

4602

T11

3422

T14

2000

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

37271

1

T10

1691

T11

1325

T14

804

rising

37260

1

T10

1690

T11

1325

T14

803

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160900

1

T10

7637

T11

5609

T14

3525

auto[1]

48934

1

T10

2225

T11

1739

T14

1062

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

37829

1

T10

1819

T11

1288

T14

778

rising

37824

1

T10

1820

T11

1287

T14

779

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160252

1

T10

7514

T11

5642

T14

3574

auto[1]

49582

1

T10

2348

T11

1706

T14

1013