Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	142482	0	0
cfg0_rd_A	2147483647	1666	0	0
compare_lower0_0_rd_A	2147483647	1502	0	0
compare_upper0_0_rd_A	2147483647	1512	0	0
ctrl_rd_A	2147483647	1521	0	0
intr_enable0_rd_A	2147483647	2448	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	142482	0	0
T10	152936	6453	0	0
T11	146824	5022	0	0
T12	134816	0	0	0
T14	135069	3705	0	0
T20	456900	0	0	0
T21	757	0	0	0
T22	280770	8564	0	0
T23	0	18669	0	0
T24	0	4920	0	0
T25	0	5491	0	0
T26	0	7800	0	0
T27	0	11225	0	0
T28	0	6258	0	0
T29	190342	0	0	0
T30	197050	0	0	0
T31	9360	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1666	0	0
T12	134816	0	0	0
T14	135069	71	0	0
T15	0	29	0	0
T18	0	6	0	0
T21	757	0	0	0
T22	280770	53	0	0
T24	0	103	0	0
T28	0	61	0	0
T29	190342	0	0	0
T30	197050	0	0	0
T31	9360	0	0	0
T32	0	33	0	0
T33	0	83	0	0
T34	0	3	0	0
T35	0	7	0	0
T36	505175	0	0	0
T37	401113	0	0	0
T38	419167	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1502	0	0
T12	134816	0	0	0
T14	135069	82	0	0
T15	0	30	0	0
T18	0	8	0	0
T21	757	0	0	0
T22	280770	66	0	0
T24	0	79	0	0
T28	0	43	0	0
T29	190342	0	0	0
T30	197050	0	0	0
T31	9360	0	0	0
T32	0	60	0	0
T33	0	122	0	0
T34	0	5	0	0
T35	0	15	0	0
T36	505175	0	0	0
T37	401113	0	0	0
T38	419167	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1512	0	0
T12	134816	0	0	0
T14	135069	76	0	0
T15	0	48	0	0
T18	0	7	0	0
T21	757	0	0	0
T22	280770	37	0	0
T24	0	91	0	0
T28	0	71	0	0
T29	190342	0	0	0
T30	197050	0	0	0
T31	9360	0	0	0
T32	0	36	0	0
T33	0	123	0	0
T34	0	8	0	0
T35	0	8	0	0
T36	505175	0	0	0
T37	401113	0	0	0
T38	419167	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1521	0	0
T12	134816	0	0	0
T14	135069	57	0	0
T15	0	46	0	0
T18	0	15	0	0
T21	757	0	0	0
T22	280770	30	0	0
T24	0	73	0	0
T28	0	56	0	0
T29	190342	0	0	0
T30	197050	0	0	0
T31	9360	0	0	0
T32	0	59	0	0
T33	0	110	0	0
T35	0	5	0	0
T36	505175	0	0	0
T37	401113	0	0	0
T38	419167	0	0	0
T39	0	15	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2448	0	0
T12	134816	0	0	0
T14	135069	221	0	0
T21	757	0	0	0
T22	280770	86	0	0
T24	0	169	0	0
T28	0	98	0	0
T29	190342	0	0	0
T30	197050	0	0	0
T31	9360	0	0	0
T32	0	62	0	0
T36	505175	0	0	0
T37	401113	0	0	0
T38	419167	0	0	0
T40	0	59	0	0
T41	0	62	0	0
T42	0	38	0	0
T43	0	35	0	0
T44	0	19	0	0