Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67769050	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

67870368

1

T1

2093

T2

1041

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	135528005	1			T1	653		T2	2114		T3	1
values[0x0]	53754	1			T1	793		T2	14		T5	1
values[0x1]	57659	1			T1	941		T2	14		T5	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54153331	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

81486087

1

T1

2223

T2

1237

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	390862	1			T2	4		T5	13		T7	47
valid_sources[0x01]	388538	1			T1	3		T2	6		T5	9
valid_sources[0x02]	389806	1			T1	6		T2	4		T5	10
valid_sources[0x03]	388859	1			T2	27		T5	10		T7	36
valid_sources[0x04]	403492	1			T2	11		T5	14		T7	35
valid_sources[0x05]	389374	1			T2	15		T5	10		T7	39
valid_sources[0x06]	389049	1			T1	30		T2	9		T5	10
valid_sources[0x07]	444933	1			T1	2		T2	3		T5	16
valid_sources[0x08]	389191	1			T1	17		T2	19		T5	18
valid_sources[0x09]	808133	1			T1	13		T2	6		T5	3
valid_sources[0x0a]	386451	1			T1	33		T5	18		T7	36
valid_sources[0x0b]	895549	1			T2	1		T5	11		T7	41
valid_sources[0x0c]	2093510	1			T1	4		T2	1		T5	9
valid_sources[0x0d]	2032338	1			T1	10		T2	8		T5	17
valid_sources[0x0e]	391801	1			T1	10		T2	8		T5	11
valid_sources[0x0f]	390570	1			T1	27		T2	3		T5	11
valid_sources[0x10]	391292	1			T1	7		T2	5		T5	13
valid_sources[0x11]	387458	1			T1	10		T2	16		T5	12
valid_sources[0x12]	388798	1			T1	1		T2	15		T5	17
valid_sources[0x13]	388804	1			T1	5		T2	6		T5	9
valid_sources[0x14]	389388	1			T1	4		T2	3		T5	19
valid_sources[0x15]	1353055	1			T2	4		T5	12		T7	41
valid_sources[0x16]	471365	1			T2	7		T5	14		T7	42
valid_sources[0x17]	388354	1			T1	42		T2	1		T5	16
valid_sources[0x18]	385924	1			T1	6		T2	12		T5	18
valid_sources[0x19]	389541	1			T2	15		T5	10		T7	35
valid_sources[0x1a]	405993	1			T1	11		T2	12		T5	8
valid_sources[0x1b]	533866	1			T1	16		T2	1		T5	16
valid_sources[0x1c]	1808481	1			T1	3		T2	7		T5	9
valid_sources[0x1d]	528689	1			T1	6		T2	16		T5	10
valid_sources[0x1e]	390686	1			T2	5		T5	12		T7	40
valid_sources[0x1f]	422262	1			T2	9		T5	12		T7	34
valid_sources[0x20]	388028	1			T1	25		T2	4		T5	17
valid_sources[0x21]	388807	1			T1	9		T2	9		T5	15
valid_sources[0x22]	390767	1			T1	6		T2	6		T5	20
valid_sources[0x23]	388734	1			T2	6		T5	18		T7	29
valid_sources[0x24]	389592	1			T1	5		T2	8		T5	12
valid_sources[0x25]	388918	1			T2	17		T5	19		T7	45
valid_sources[0x26]	387938	1			T1	19		T2	14		T5	14
valid_sources[0x27]	388520	1			T1	13		T2	10		T5	16
valid_sources[0x28]	542875	1			T1	4		T2	11		T5	11
valid_sources[0x29]	390054	1			T1	16		T2	11		T5	14
valid_sources[0x2a]	388590	1			T2	8		T5	15		T7	36
valid_sources[0x2b]	387967	1			T1	1		T2	6		T5	17
valid_sources[0x2c]	440051	1			T1	6		T2	20		T5	15
valid_sources[0x2d]	463797	1			T1	5		T2	4		T5	10
valid_sources[0x2e]	389361	1			T1	15		T2	17		T5	12
valid_sources[0x2f]	386572	1			T1	7		T2	4		T5	17
valid_sources[0x30]	411283	1			T1	12		T2	17		T5	9
valid_sources[0x31]	397094	1			T1	3		T2	13		T5	15
valid_sources[0x32]	499017	1			T2	10		T5	10		T7	37
valid_sources[0x33]	613030	1			T1	10		T2	3		T5	15
valid_sources[0x34]	389001	1			T1	6		T2	15		T5	15
valid_sources[0x35]	390024	1			T1	23		T2	3		T5	12
valid_sources[0x36]	395566	1			T1	1		T2	6		T5	15
valid_sources[0x37]	437541	1			T1	1		T2	8		T5	8
valid_sources[0x38]	401187	1			T1	22		T2	3		T5	13
valid_sources[0x39]	384881	1			T1	3		T2	8		T5	18
valid_sources[0x3a]	392379	1			T1	52		T2	13		T5	16
valid_sources[0x3b]	387250	1			T1	4		T2	9		T5	15
valid_sources[0x3c]	390949	1			T2	8		T5	18		T7	34
valid_sources[0x3d]	3670388	1			T1	4		T2	11		T5	15
valid_sources[0x3e]	391601	1			T1	5		T2	10		T5	12
valid_sources[0x3f]	386504	1			T1	2		T2	2		T5	15
valid_sources[0x40]	389477	1			T1	16		T2	13		T5	15
valid_sources[0x41]	1094265	1			T1	5		T2	5		T5	10
valid_sources[0x42]	386451	1			T1	3		T2	9		T5	12
valid_sources[0x43]	390119	1			T1	9		T2	4		T5	14
valid_sources[0x44]	393553	1			T1	37		T2	14		T5	12
valid_sources[0x45]	600421	1			T2	5		T5	10		T7	45
valid_sources[0x46]	415003	1			T1	15		T2	10		T5	15
valid_sources[0x47]	390236	1			T1	1		T2	10		T5	18
valid_sources[0x48]	415682	1			T1	31		T2	5		T5	12
valid_sources[0x49]	389401	1			T1	5		T2	17		T5	13
valid_sources[0x4a]	499701	1			T1	7		T2	8		T5	13
valid_sources[0x4b]	387306	1			T1	3		T2	3		T5	14
valid_sources[0x4c]	387709	1			T1	4		T2	2		T5	7
valid_sources[0x4d]	402176	1			T1	8		T2	8		T5	12
valid_sources[0x4e]	391725	1			T1	46		T2	7		T5	12
valid_sources[0x4f]	390178	1			T2	4		T5	14		T7	40
valid_sources[0x50]	386095	1			T1	11		T2	5		T5	10
valid_sources[0x51]	388871	1			T2	10		T5	19		T7	43
valid_sources[0x52]	390723	1			T1	17		T2	6		T5	11
valid_sources[0x53]	388738	1			T1	6		T2	3		T5	13
valid_sources[0x54]	387984	1			T1	9		T2	18		T5	13
valid_sources[0x55]	388584	1			T1	10		T2	6		T5	13
valid_sources[0x56]	386400	1			T1	5		T2	3		T5	18
valid_sources[0x57]	888960	1			T1	20		T2	7		T5	16
valid_sources[0x58]	561532	1			T1	11		T2	10		T5	17
valid_sources[0x59]	1204389	1			T1	6		T2	7		T5	11
valid_sources[0x5a]	390548	1			T1	15		T2	7		T5	15
valid_sources[0x5b]	389672	1			T2	22		T5	14		T7	44
valid_sources[0x5c]	402818	1			T1	20		T2	4		T5	10
valid_sources[0x5d]	423222	1			T1	9		T2	12		T5	13
valid_sources[0x5e]	389065	1			T1	8		T2	8		T5	9
valid_sources[0x5f]	441214	1			T1	3		T2	11		T5	12
valid_sources[0x60]	390711	1			T1	11		T2	3		T5	13
valid_sources[0x61]	392182	1			T1	1		T2	2		T5	15
valid_sources[0x62]	392065	1			T1	7		T2	11		T5	16
valid_sources[0x63]	390905	1			T1	5		T2	9		T5	6
valid_sources[0x64]	391471	1			T1	19		T2	2		T5	11
valid_sources[0x65]	389065	1			T1	4		T2	7		T5	10
valid_sources[0x66]	390147	1			T2	5		T5	11		T7	37
valid_sources[0x67]	398916	1			T2	6		T5	17		T7	24
valid_sources[0x68]	939790	1			T1	5		T2	18		T5	6
valid_sources[0x69]	481253	1			T1	1		T2	5		T5	13
valid_sources[0x6a]	399999	1			T2	10		T5	11		T7	50
valid_sources[0x6b]	1381128	1			T1	14		T2	9		T5	17
valid_sources[0x6c]	389040	1			T1	9		T2	6		T5	17
valid_sources[0x6d]	397908	1			T1	7		T2	5		T5	19
valid_sources[0x6e]	389044	1			T1	2		T2	8		T5	14
valid_sources[0x6f]	389681	1			T1	15		T2	10		T5	21
valid_sources[0x70]	392810	1			T1	35		T2	11		T5	6
valid_sources[0x71]	389669	1			T1	3		T2	20		T5	9
valid_sources[0x72]	392516	1			T2	8		T5	15		T7	40
valid_sources[0x73]	387917	1			T1	3		T2	9		T5	12
valid_sources[0x74]	1246247	1			T1	1		T2	3		T5	8
valid_sources[0x75]	580753	1			T2	11		T5	12		T7	37
valid_sources[0x76]	390472	1			T1	21		T2	1		T5	13
valid_sources[0x77]	388523	1			T1	3		T2	3		T5	11
valid_sources[0x78]	385947	1			T1	9		T2	6		T5	14
valid_sources[0x79]	624669	1			T1	14		T2	10		T5	17
valid_sources[0x7a]	388227	1			T2	8		T5	15		T7	23
valid_sources[0x7b]	390567	1			T1	12		T2	12		T5	13
valid_sources[0x7c]	1865958	1			T1	18		T2	7		T5	13
valid_sources[0x7d]	390312	1			T1	18		T5	17		T7	40
valid_sources[0x7e]	390775	1			T1	3		T2	12		T5	14
valid_sources[0x7f]	386698	1			T1	16		T2	5		T5	14
valid_sources[0x80]	388767	1			T1	8		T2	8		T5	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67774354

1

T1

541

T2

1024

T3

1

values[0x0]

all_enables

biggest_size

48896

1

T1

767

T2

9

T5

1

values[0x1]

all_enables

biggest_size

47118

1

T1

785

T2

8

T5

4