Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	68442361	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

68540120

1

T1

1

T3

105

T7

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136888126	1			T1	1		T2	1		T3	123
values[0x0]	45932	1			T3	27		T7	6		T8	773
values[0x1]	48423	1			T3	20		T7	4		T8	857

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54696134	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

82286347

1

T1

1

T2

1

T3

114

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	421419	1			T3	4		T8	17		T10	13
valid_sources[0x01]	432161	1			T8	1		T9	5		T10	1
valid_sources[0x02]	457036	1			T9	6		T10	19		T21	2
valid_sources[0x03]	422465	1			T8	6		T9	10		T10	14
valid_sources[0x04]	424862	1			T8	10		T9	18		T21	3
valid_sources[0x05]	422946	1			T8	3		T9	22		T10	6
valid_sources[0x06]	424477	1			T8	3		T9	5		T10	11
valid_sources[0x07]	423954	1			T9	57		T14	13		T11	14
valid_sources[0x08]	3169936	1			T3	11		T7	3		T9	1
valid_sources[0x09]	422892	1			T8	6		T10	8		T21	1
valid_sources[0x0a]	423520	1			T9	43		T10	6		T11	16
valid_sources[0x0b]	420833	1			T9	2		T10	8		T21	1
valid_sources[0x0c]	420433	1			T8	24		T9	20		T10	7
valid_sources[0x0d]	423480	1			T9	6		T10	7		T21	1
valid_sources[0x0e]	424914	1			T8	22		T9	27		T10	4
valid_sources[0x0f]	417213	1			T8	37		T9	5		T10	3
valid_sources[0x10]	420709	1			T9	2		T10	24		T14	52
valid_sources[0x11]	423100	1			T8	1		T9	10		T10	12
valid_sources[0x12]	447589	1			T8	2		T9	11		T10	5
valid_sources[0x13]	423750	1			T3	6		T8	4		T9	1
valid_sources[0x14]	420756	1			T8	5		T9	17		T10	4
valid_sources[0x15]	422014	1			T9	6		T10	11		T21	3
valid_sources[0x16]	576447	1			T9	5		T10	4		T22	1
valid_sources[0x17]	972224	1			T8	34		T10	9		T11	16
valid_sources[0x18]	461023	1			T9	43		T10	2		T21	1
valid_sources[0x19]	425380	1			T8	12		T9	53		T10	3
valid_sources[0x1a]	420191	1			T9	8		T10	7		T21	2
valid_sources[0x1b]	777011	1			T8	38		T9	25		T10	3
valid_sources[0x1c]	417746	1			T7	3		T10	5		T21	1
valid_sources[0x1d]	441070	1			T8	9		T9	1		T21	1
valid_sources[0x1e]	417937	1			T8	7		T10	8		T21	1
valid_sources[0x1f]	1926774	1			T7	4		T8	40		T9	5
valid_sources[0x20]	417475	1			T8	2		T9	23		T10	7
valid_sources[0x21]	421763	1			T8	26		T9	25		T10	7
valid_sources[0x22]	421979	1			T8	11		T9	4		T10	5
valid_sources[0x23]	422932	1			T9	9		T10	6		T11	4
valid_sources[0x24]	419306	1			T8	8		T9	19		T10	4
valid_sources[0x25]	426038	1			T9	26		T10	2		T21	1
valid_sources[0x26]	423281	1			T8	1		T10	8		T21	1
valid_sources[0x27]	1068472	1			T7	2		T8	4		T9	18
valid_sources[0x28]	423295	1			T8	2		T9	8		T10	1
valid_sources[0x29]	1148869	1			T9	12		T10	6		T21	1
valid_sources[0x2a]	421298	1			T8	3		T9	9		T10	11
valid_sources[0x2b]	424213	1			T7	5		T9	13		T10	4
valid_sources[0x2c]	420843	1			T8	4		T10	11		T11	16
valid_sources[0x2d]	424060	1			T3	2		T9	43		T10	3
valid_sources[0x2e]	3221320	1			T10	3		T21	1		T14	253
valid_sources[0x2f]	422935	1			T8	40		T9	17		T10	5
valid_sources[0x30]	421435	1			T8	22		T9	4		T10	11
valid_sources[0x31]	422755	1			T8	5		T9	27		T10	9
valid_sources[0x32]	588744	1			T3	10		T10	3		T14	103
valid_sources[0x33]	419516	1			T9	12		T10	7		T21	1
valid_sources[0x34]	431354	1			T8	9		T9	15		T10	9
valid_sources[0x35]	436567	1			T9	13		T21	1		T11	22
valid_sources[0x36]	423909	1			T8	6		T10	8		T21	4
valid_sources[0x37]	424065	1			T3	5		T9	17		T10	11
valid_sources[0x38]	427238	1			T8	2		T9	7		T10	7
valid_sources[0x39]	426443	1			T8	1		T9	41		T10	2
valid_sources[0x3a]	418679	1			T8	20		T9	14		T10	11
valid_sources[0x3b]	422967	1			T8	9		T9	16		T10	4
valid_sources[0x3c]	419857	1			T9	37		T10	4		T21	1
valid_sources[0x3d]	420034	1			T3	9		T8	15		T9	15
valid_sources[0x3e]	419796	1			T3	1		T9	6		T10	2
valid_sources[0x3f]	419939	1			T8	17		T9	40		T10	9
valid_sources[0x40]	664463	1			T9	11		T10	4		T21	1
valid_sources[0x41]	692409	1			T8	1		T10	9		T11	11
valid_sources[0x42]	422753	1			T8	40		T9	3		T11	7
valid_sources[0x43]	423282	1			T9	51		T10	13		T11	16
valid_sources[0x44]	2132769	1			T9	59		T10	17		T11	10
valid_sources[0x45]	418810	1			T8	9		T9	36		T10	12
valid_sources[0x46]	426725	1			T8	12		T10	5		T14	18
valid_sources[0x47]	423531	1			T8	6		T9	73		T10	10
valid_sources[0x48]	421695	1			T9	22		T10	2		T11	12
valid_sources[0x49]	426440	1			T9	18		T10	8		T21	1
valid_sources[0x4a]	421824	1			T8	7		T9	16		T10	8
valid_sources[0x4b]	423980	1			T9	18		T10	3		T14	80
valid_sources[0x4c]	421403	1			T8	28		T9	14		T10	7
valid_sources[0x4d]	982005	1			T8	3		T9	38		T10	4
valid_sources[0x4e]	458760	1			T8	13		T9	13		T10	1
valid_sources[0x4f]	420413	1			T8	9		T9	7		T10	5
valid_sources[0x50]	420752	1			T9	8		T10	7		T21	1
valid_sources[0x51]	476976	1			T9	19		T10	2		T13	53522
valid_sources[0x52]	418835	1			T9	12		T10	10		T11	14
valid_sources[0x53]	420931	1			T8	13		T9	36		T10	8
valid_sources[0x54]	514904	1			T9	7		T10	20		T11	22
valid_sources[0x55]	3385901	1			T7	6		T8	10		T9	15
valid_sources[0x56]	3680240	1			T8	16		T9	16		T10	5
valid_sources[0x57]	421006	1			T8	2		T10	7		T21	1
valid_sources[0x58]	421206	1			T3	5		T9	11		T10	8
valid_sources[0x59]	516282	1			T9	34		T10	8		T14	64
valid_sources[0x5a]	423028	1			T8	10		T9	12		T10	10
valid_sources[0x5b]	421253	1			T9	58		T10	7		T21	2
valid_sources[0x5c]	422723	1			T8	5		T9	2		T10	5
valid_sources[0x5d]	421147	1			T9	22		T10	3		T11	16
valid_sources[0x5e]	421326	1			T8	28		T9	55		T21	1
valid_sources[0x5f]	424095	1			T8	11		T9	17		T10	2
valid_sources[0x60]	419451	1			T9	4		T10	4		T14	54
valid_sources[0x61]	423489	1			T8	11		T9	11		T10	5
valid_sources[0x62]	418577	1			T8	38		T9	23		T10	7
valid_sources[0x63]	864966	1			T8	20		T9	5		T10	6
valid_sources[0x64]	423257	1			T9	7		T10	10		T21	1
valid_sources[0x65]	422983	1			T8	7		T9	18		T10	14
valid_sources[0x66]	420588	1			T9	13		T10	5		T14	18
valid_sources[0x67]	428511	1			T10	6		T11	15		T15	4
valid_sources[0x68]	1062284	1			T9	40		T10	5		T21	1
valid_sources[0x69]	423452	1			T8	55		T9	10		T10	4
valid_sources[0x6a]	424560	1			T9	1		T10	2		T11	12
valid_sources[0x6b]	426569	1			T8	6		T9	3		T10	9
valid_sources[0x6c]	882377	1			T3	4		T8	3		T9	1
valid_sources[0x6d]	421048	1			T8	8		T9	56		T10	1
valid_sources[0x6e]	422419	1			T9	38		T10	2		T11	11
valid_sources[0x6f]	425418	1			T9	13		T10	4		T21	2
valid_sources[0x70]	425159	1			T5	1		T8	2		T9	36
valid_sources[0x71]	439546	1			T8	10		T10	5		T14	152
valid_sources[0x72]	770166	1			T3	9		T9	39		T10	6
valid_sources[0x73]	424001	1			T8	3		T9	16		T10	4
valid_sources[0x74]	421610	1			T10	7		T21	1		T14	121
valid_sources[0x75]	1245119	1			T8	22		T9	21		T21	1
valid_sources[0x76]	424032	1			T9	19		T10	13		T21	1
valid_sources[0x77]	420264	1			T3	28		T8	8		T10	18
valid_sources[0x78]	813302	1			T9	8		T10	3		T21	1
valid_sources[0x79]	423581	1			T9	20		T10	4		T14	66
valid_sources[0x7a]	422716	1			T8	7		T10	13		T21	2
valid_sources[0x7b]	421027	1			T8	48		T9	5		T10	1
valid_sources[0x7c]	421884	1			T9	1		T14	100		T11	6
valid_sources[0x7d]	459712	1			T8	17		T9	8		T10	1
valid_sources[0x7e]	1845309	1			T9	5		T10	6		T21	2
valid_sources[0x7f]	422419	1			T8	2		T9	2		T10	1
valid_sources[0x80]	421854	1			T8	2		T9	43		T10	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68460166

1

T1

1

T3

72

T7

18

values[0x0]

all_enables

biggest_size

40806

1

T3

20

T7

4

T8

760

values[0x1]

all_enables

biggest_size

39148

1

T3

13

T7

2

T8

771