Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	89900	0	0
cfg0_rd_A	2147483647	2963	0	0
compare_lower0_0_rd_A	2147483647	2638	0	0
compare_upper0_0_rd_A	2147483647	2560	0	0
ctrl_rd_A	2147483647	2768	0	0
intr_enable0_rd_A	2147483647	3808	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	89900	0	0
T8	84869	2471	0	0
T9	161168	0	0	0
T10	961670	0	0	0
T11	105706	3742	0	0
T12	0	8374	0	0
T13	500558	0	0	0
T14	460853	0	0	0
T15	226120	0	0	0
T21	25697	0	0	0
T22	3972	0	0	0
T23	0	8249	0	0
T24	0	5101	0	0
T25	0	5013	0	0
T26	0	15400	0	0
T27	0	7871	0	0
T28	0	6143	0	0
T29	0	7101	0	0
T30	709458	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2963	0	0
T8	84869	26	0	0
T9	161168	0	0	0
T10	961670	0	0	0
T11	105706	0	0	0
T13	500558	0	0	0
T14	460853	0	0	0
T15	226120	0	0	0
T17	0	147	0	0
T18	0	169	0	0
T21	25697	0	0	0
T22	3972	0	0	0
T23	0	75	0	0
T24	0	65	0	0
T30	709458	0	0	0
T31	0	23	0	0
T32	0	15	0	0
T33	0	104	0	0
T34	0	12	0	0
T35	0	458	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2638	0	0
T8	84869	35	0	0
T9	161168	0	0	0
T10	961670	0	0	0
T11	105706	0	0	0
T13	500558	0	0	0
T14	460853	0	0	0
T15	226120	0	0	0
T17	0	101	0	0
T21	25697	0	0	0
T22	3972	0	0	0
T23	0	85	0	0
T24	0	96	0	0
T30	709458	0	0	0
T31	0	35	0	0
T32	0	16	0	0
T33	0	89	0	0
T34	0	3	0	0
T35	0	434	0	0
T36	0	6	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2560	0	0
T8	84869	61	0	0
T9	161168	0	0	0
T10	961670	0	0	0
T11	105706	0	0	0
T13	500558	0	0	0
T14	460853	0	0	0
T15	226120	0	0	0
T17	0	118	0	0
T21	25697	0	0	0
T22	3972	0	0	0
T23	0	79	0	0
T24	0	91	0	0
T30	709458	0	0	0
T31	0	38	0	0
T32	0	21	0	0
T33	0	77	0	0
T34	0	16	0	0
T35	0	433	0	0
T36	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2768	0	0
T8	84869	45	0	0
T9	161168	0	0	0
T10	961670	0	0	0
T11	105706	0	0	0
T13	500558	0	0	0
T14	460853	0	0	0
T15	226120	0	0	0
T17	0	119	0	0
T21	25697	0	0	0
T22	3972	0	0	0
T23	0	64	0	0
T24	0	96	0	0
T30	709458	0	0	0
T31	0	40	0	0
T32	0	7	0	0
T33	0	81	0	0
T34	0	14	0	0
T35	0	512	0	0
T37	0	16	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3808	0	0
T8	84869	80	0	0
T9	161168	0	0	0
T10	961670	0	0	0
T11	105706	0	0	0
T13	500558	0	0	0
T14	460853	0	0	0
T15	226120	0	0	0
T21	25697	0	0	0
T22	3972	0	0	0
T23	0	110	0	0
T24	0	169	0	0
T30	709458	0	0	0
T31	0	68	0	0
T38	0	12	0	0
T39	0	68	0	0
T40	0	140	0	0
T41	0	82	0	0
T42	0	120	0	0
T43	0	48	0	0