Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	68365889	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

68513807

1

T1

1

T5

1

T6

1640

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136749082	1			T1	1		T2	1		T3	1
values[0x0]	63248	1			T6	20		T7	1855		T8	4640
values[0x1]	67366	1			T6	19		T7	2019		T8	4902

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54631018	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

82248678

1

T1

1

T5

1

T6

1989

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	386362	1			T6	16		T7	39		T8	55
valid_sources[0x01]	385193	1			T6	21		T7	21		T8	45
valid_sources[0x02]	382313	1			T6	15		T7	25		T8	62
valid_sources[0x03]	385223	1			T6	12		T7	22		T8	67
valid_sources[0x04]	383765	1			T6	21		T7	23		T8	52
valid_sources[0x05]	383801	1			T6	14		T7	19		T8	52
valid_sources[0x06]	382703	1			T6	7		T7	25		T8	38
valid_sources[0x07]	383169	1			T6	15		T7	29		T8	51
valid_sources[0x08]	383603	1			T6	9		T7	25		T8	59
valid_sources[0x09]	385319	1			T6	14		T7	17		T8	61
valid_sources[0x0a]	726625	1			T6	24		T7	15		T8	43
valid_sources[0x0b]	382420	1			T6	10		T7	25		T8	40
valid_sources[0x0c]	384354	1			T6	7		T7	24		T8	50
valid_sources[0x0d]	3021323	1			T6	12		T7	18		T8	45
valid_sources[0x0e]	493811	1			T6	20		T7	23		T8	59
valid_sources[0x0f]	818805	1			T6	11		T7	14		T8	58
valid_sources[0x10]	379982	1			T6	21		T7	27		T8	36
valid_sources[0x11]	381963	1			T6	13		T7	9		T8	50
valid_sources[0x12]	389139	1			T6	8		T7	29		T8	53
valid_sources[0x13]	380297	1			T6	15		T7	23		T8	53
valid_sources[0x14]	382182	1			T6	15		T7	20		T8	51
valid_sources[0x15]	1335780	1			T6	12		T7	18		T8	46
valid_sources[0x16]	381726	1			T6	15		T7	15		T8	46
valid_sources[0x17]	384178	1			T6	20		T7	23		T8	62
valid_sources[0x18]	382438	1			T6	13		T7	26		T8	60
valid_sources[0x19]	385454	1			T6	9		T7	14		T8	48
valid_sources[0x1a]	381781	1			T6	19		T7	10		T8	64
valid_sources[0x1b]	381379	1			T6	9		T7	16		T8	59
valid_sources[0x1c]	392808	1			T6	19		T7	21		T8	57
valid_sources[0x1d]	381893	1			T6	8		T7	20		T8	44
valid_sources[0x1e]	382025	1			T6	6		T7	16		T8	41
valid_sources[0x1f]	1144816	1			T6	13		T7	14		T8	62
valid_sources[0x20]	383914	1			T6	16		T7	17		T8	57
valid_sources[0x21]	383667	1			T6	16		T7	28		T8	61
valid_sources[0x22]	382014	1			T6	11		T7	23		T8	57
valid_sources[0x23]	380920	1			T6	9		T7	31		T8	46
valid_sources[0x24]	384511	1			T6	14		T7	23		T8	58
valid_sources[0x25]	411845	1			T6	8		T7	23		T8	48
valid_sources[0x26]	381535	1			T6	5		T7	24		T8	45
valid_sources[0x27]	381045	1			T6	16		T7	17		T8	55
valid_sources[0x28]	382108	1			T6	6		T7	16		T8	49
valid_sources[0x29]	404417	1			T6	7		T7	25		T8	59
valid_sources[0x2a]	382874	1			T6	13		T7	28		T8	49
valid_sources[0x2b]	381368	1			T6	12		T7	19		T8	53
valid_sources[0x2c]	380227	1			T6	6		T7	28		T8	55
valid_sources[0x2d]	383867	1			T6	16		T7	14		T8	46
valid_sources[0x2e]	384260	1			T6	12		T7	24		T8	55
valid_sources[0x2f]	384205	1			T6	10		T7	27		T8	58
valid_sources[0x30]	381018	1			T6	13		T7	22		T8	57
valid_sources[0x31]	578830	1			T6	13		T7	22		T8	36
valid_sources[0x32]	658581	1			T6	11		T7	18		T8	71
valid_sources[0x33]	379492	1			T6	19		T7	23		T8	61
valid_sources[0x34]	382820	1			T6	15		T7	22		T8	48
valid_sources[0x35]	2549148	1			T6	13		T7	24		T8	67
valid_sources[0x36]	385552	1			T6	9		T7	12		T8	56
valid_sources[0x37]	379705	1			T6	18		T7	32		T8	66
valid_sources[0x38]	751272	1			T6	22		T7	20		T8	51
valid_sources[0x39]	473800	1			T6	10		T7	15		T8	51
valid_sources[0x3a]	409656	1			T6	11		T7	13		T8	52
valid_sources[0x3b]	406659	1			T6	9		T7	24		T8	54
valid_sources[0x3c]	381716	1			T6	7		T7	26		T8	54
valid_sources[0x3d]	383537	1			T6	20		T7	36		T8	58
valid_sources[0x3e]	391161	1			T6	12		T7	23		T8	35
valid_sources[0x3f]	524567	1			T6	15		T7	18		T8	53
valid_sources[0x40]	381469	1			T6	5		T7	20		T8	57
valid_sources[0x41]	7527650	1			T6	12		T7	14		T8	59
valid_sources[0x42]	382705	1			T6	20		T7	18		T8	37
valid_sources[0x43]	676225	1			T6	15		T7	25		T8	58
valid_sources[0x44]	387328	1			T6	10		T7	24		T8	57
valid_sources[0x45]	773233	1			T6	6		T7	29		T8	58
valid_sources[0x46]	382178	1			T6	20		T7	32		T8	45
valid_sources[0x47]	650222	1			T6	11		T7	29		T8	57
valid_sources[0x48]	383121	1			T6	13		T7	24		T8	55
valid_sources[0x49]	1146773	1			T6	16		T7	21		T8	61
valid_sources[0x4a]	382728	1			T6	9		T7	25		T8	55
valid_sources[0x4b]	380705	1			T6	18		T7	15		T8	66
valid_sources[0x4c]	381432	1			T6	14		T7	30		T8	60
valid_sources[0x4d]	384300	1			T6	14		T7	25		T8	43
valid_sources[0x4e]	380971	1			T6	15		T7	15		T8	60
valid_sources[0x4f]	478711	1			T6	20		T7	17		T8	74
valid_sources[0x50]	384057	1			T6	14		T7	21		T8	33
valid_sources[0x51]	381014	1			T6	17		T7	21		T8	51
valid_sources[0x52]	384449	1			T6	3		T7	10		T8	49
valid_sources[0x53]	384815	1			T6	5		T7	26		T8	59
valid_sources[0x54]	629813	1			T6	2		T7	18		T8	47
valid_sources[0x55]	393352	1			T6	11		T7	13		T8	46
valid_sources[0x56]	379064	1			T6	18		T7	24		T8	57
valid_sources[0x57]	382167	1			T6	12		T7	28		T8	69
valid_sources[0x58]	380661	1			T6	27		T7	27		T8	57
valid_sources[0x59]	381749	1			T6	15		T7	16		T8	62
valid_sources[0x5a]	428210	1			T1	1		T6	11		T7	13
valid_sources[0x5b]	386699	1			T6	7		T7	15		T8	55
valid_sources[0x5c]	866625	1			T6	5		T7	20		T8	51
valid_sources[0x5d]	381955	1			T6	16		T7	11		T8	49
valid_sources[0x5e]	384452	1			T6	14		T7	26		T8	43
valid_sources[0x5f]	387920	1			T6	11		T7	15		T8	57
valid_sources[0x60]	383407	1			T6	14		T7	18		T8	40
valid_sources[0x61]	382003	1			T6	19		T7	18		T8	53
valid_sources[0x62]	472029	1			T6	12		T7	21		T8	50
valid_sources[0x63]	1033126	1			T6	16		T7	19		T8	50
valid_sources[0x64]	384632	1			T6	6		T7	28		T8	53
valid_sources[0x65]	385658	1			T6	14		T7	21		T8	57
valid_sources[0x66]	381960	1			T6	21		T7	32		T8	43
valid_sources[0x67]	378615	1			T6	12		T7	21		T8	54
valid_sources[0x68]	382713	1			T6	8		T7	16		T8	57
valid_sources[0x69]	380419	1			T6	14		T7	17		T8	42
valid_sources[0x6a]	384419	1			T6	16		T7	17		T8	53
valid_sources[0x6b]	379245	1			T6	17		T7	17		T8	64
valid_sources[0x6c]	384700	1			T6	5		T7	33		T8	48
valid_sources[0x6d]	419862	1			T6	15		T7	33		T8	65
valid_sources[0x6e]	383354	1			T6	12		T7	15		T8	60
valid_sources[0x6f]	385543	1			T6	14		T7	32		T8	53
valid_sources[0x70]	386606	1			T6	10		T7	23		T8	55
valid_sources[0x71]	392722	1			T6	12		T7	24		T8	67
valid_sources[0x72]	421740	1			T6	16		T7	15		T8	54
valid_sources[0x73]	419543	1			T6	12		T7	13		T8	59
valid_sources[0x74]	383659	1			T6	13		T7	25		T8	45
valid_sources[0x75]	385762	1			T6	12		T7	23		T8	38
valid_sources[0x76]	384311	1			T6	13		T7	19		T8	50
valid_sources[0x77]	666374	1			T6	11		T7	14		T8	58
valid_sources[0x78]	381979	1			T6	13		T7	21		T8	51
valid_sources[0x79]	381722	1			T6	13		T7	17		T8	47
valid_sources[0x7a]	384177	1			T6	22		T7	13		T8	51
valid_sources[0x7b]	382129	1			T6	8		T7	8		T8	51
valid_sources[0x7c]	380086	1			T6	14		T7	20		T8	50
valid_sources[0x7d]	384320	1			T6	5		T7	19		T8	43
valid_sources[0x7e]	480253	1			T6	8		T7	25		T8	49
valid_sources[0x7f]	380098	1			T6	7		T7	31		T8	61
valid_sources[0x80]	382160	1			T6	11		T7	23		T8	49

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68400329

1

T1

1

T5

1

T6

1614

values[0x0]

all_enables

biggest_size

57814

1

T6

14

T7

1829

T8

4546

values[0x1]

all_enables

biggest_size

55664

1

T6

12

T7

1807

T8

4432