Unified Coverage Report :: Module :: rv_timer_reg_top

Module : rv_timer_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.78	99.24	99.64	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_cfg0_prescale	100.00	100.00	100.00			100.00
u_cfg0_step	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_compare_lower0_0	100.00	100.00	100.00			100.00
u_compare_lower0_00_qe	100.00	100.00				100.00
u_compare_upper0_0	100.00	100.00	100.00			100.00
u_compare_upper0_00_qe	100.00	100.00				100.00
u_ctrl	100.00	100.00	100.00			100.00
u_intr_enable0	100.00	100.00	100.00			100.00
u_intr_state0	100.00	100.00	100.00			100.00
u_intr_test0	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.97	97.14	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_timer_v_lower0	100.00	100.00	100.00			100.00
u_timer_v_upper0	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_timer_reg_top

	Line No.	Total	Covered	Percent
TOTAL		75	75	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
ALWAYS	479	11	11	100.00
CONT_ASSIGN	492	1	1	100.00
ALWAYS	496	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
ALWAYS	545	11	11	100.00
ALWAYS	560	13	13	100.00
CONT_ASSIGN	614	0	0
CONT_ASSIGN	622	1	1	100.00
CONT_ASSIGN	623	1	1	100.00

67                        always_ff @(posedge clk_i or negedge rst_ni) begin
68         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
69         1/1                err_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (intg_err || reg_we_err) begin
           Tests:       T1 T2 T3 
71         1/1                err_q <= 1'b1;
           Tests:       T1 T2 T3 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // integrity error output is permanent and should be used for alert generation
76                        // register errors are transactional
77         1/1            assign intg_err_o = err_q | intg_err | reg_we_err;
           Tests:       T1 T2 T3 
78                      
79                        // outgoing integrity generation
80                        tlul_pkg::tl_d2h_t tl_o_pre;
81                        tlul_rsp_intg_gen #(
82                          .EnableRspIntgGen(1),
83                          .EnableDataIntgGen(1)
84                        ) u_rsp_intg_gen (
85                          .tl_i(tl_o_pre),
86                          .tl_o(tl_o)
87                        );
88                      
89         1/1            assign tl_reg_h2d = tl_i;
           Tests:       T1 T2 T3 
90         1/1            assign tl_o_pre   = tl_reg_d2h;
           Tests:       T1 T2 T3 
91                      
92                        tlul_adapter_reg #(
93                          .RegAw(AW),
94                          .RegDw(DW),
95                          .EnableDataIntgGen(0)
96                        ) u_reg_if (
97                          .clk_i  (clk_i),
98                          .rst_ni (rst_ni),
99                      
100                         .tl_i (tl_reg_h2d),
101                         .tl_o (tl_reg_d2h),
102                     
103                         .en_ifetch_i(prim_mubi_pkg::MuBi4False),
104                         .intg_error_o(),
105                     
106                         .we_o    (reg_we),
107                         .re_o    (reg_re),
108                         .addr_o  (reg_addr),
109                         .wdata_o (reg_wdata),
110                         .be_o    (reg_be),
111                         .busy_i  (reg_busy),
112                         .rdata_i (reg_rdata),
113                         .error_i (reg_error)
114                       );
115                     
116                       // cdc oversampling signals
117                     
118        1/1            assign reg_rdata = reg_rdata_next ;
           Tests:       T1 T2 T3 
119        1/1            assign reg_error = addrmiss | wr_err | intg_err;
           Tests:       T7 T8 T13 
120                     
121                       // Define SW related signals
122                       // Format: <reg>_<field>_{wd|we|qs}
123                       //        or <reg>_{wd|we|qs} if field == 1 or 0
124                       logic alert_test_we;
125                       logic alert_test_wd;
126                       logic ctrl_we;
127                       logic ctrl_qs;
128                       logic ctrl_wd;
129                       logic intr_enable0_we;
130                       logic intr_enable0_qs;
131                       logic intr_enable0_wd;
132                       logic intr_state0_we;
133                       logic intr_state0_qs;
134                       logic intr_state0_wd;
135                       logic intr_test0_we;
136                       logic intr_test0_wd;
137                       logic cfg0_we;
138                       logic [11:0] cfg0_prescale_qs;
139                       logic [11:0] cfg0_prescale_wd;
140                       logic [7:0] cfg0_step_qs;
141                       logic [7:0] cfg0_step_wd;
142                       logic timer_v_lower0_we;
143                       logic [31:0] timer_v_lower0_qs;
144                       logic [31:0] timer_v_lower0_wd;
145                       logic timer_v_upper0_we;
146                       logic [31:0] timer_v_upper0_qs;
147                       logic [31:0] timer_v_upper0_wd;
148                       logic compare_lower0_0_we;
149                       logic [31:0] compare_lower0_0_qs;
150                       logic [31:0] compare_lower0_0_wd;
151                       logic compare_upper0_0_we;
152                       logic [31:0] compare_upper0_0_qs;
153                       logic [31:0] compare_upper0_0_wd;
154                     
155                       // Register instances
156                       // R[alert_test]: V(True)
157                       logic alert_test_qe;
158                       logic [0:0] alert_test_flds_we;
159        1/1            assign alert_test_qe = &alert_test_flds_we;
           Tests:       T7 T8 T13 
160                       prim_subreg_ext #(
161                         .DW    (1)
162                       ) u_alert_test (
163                         .re     (1'b0),
164                         .we     (alert_test_we),
165                         .wd     (alert_test_wd),
166                         .d      ('0),
167                         .qre    (),
168                         .qe     (alert_test_flds_we[0]),
169                         .q      (reg2hw.alert_test.q),
170                         .ds     (),
171                         .qs     ()
172                       );
173        1/1            assign reg2hw.alert_test.qe = alert_test_qe;
           Tests:       T7 T8 T13 
174                     
175                     
176                       // Subregister 0 of Multireg ctrl
177                       // R[ctrl]: V(False)
178                       prim_subreg #(
179                         .DW      (1),
180                         .SwAccess(prim_subreg_pkg::SwAccessRW),
181                         .RESVAL  (1'h0),
182                         .Mubi    (1'b0)
183                       ) u_ctrl (
184                         .clk_i   (clk_i),
185                         .rst_ni  (rst_ni),
186                     
187                         // from register interface
188                         .we     (ctrl_we),
189                         .wd     (ctrl_wd),
190                     
191                         // from internal hardware
192                         .de     (1'b0),
193                         .d      ('0),
194                     
195                         // to internal hardware
196                         .qe     (),
197                         .q      (reg2hw.ctrl[0].q),
198                         .ds     (),
199                     
200                         // to register interface (read)
201                         .qs     (ctrl_qs)
202                       );
203                     
204                     
205                       // Subregister 0 of Multireg intr_enable0
206                       // R[intr_enable0]: V(False)
207                       prim_subreg #(
208                         .DW      (1),
209                         .SwAccess(prim_subreg_pkg::SwAccessRW),
210                         .RESVAL  (1'h0),
211                         .Mubi    (1'b0)
212                       ) u_intr_enable0 (
213                         .clk_i   (clk_i),
214                         .rst_ni  (rst_ni),
215                     
216                         // from register interface
217                         .we     (intr_enable0_we),
218                         .wd     (intr_enable0_wd),
219                     
220                         // from internal hardware
221                         .de     (1'b0),
222                         .d      ('0),
223                     
224                         // to internal hardware
225                         .qe     (),
226                         .q      (reg2hw.intr_enable0[0].q),
227                         .ds     (),
228                     
229                         // to register interface (read)
230                         .qs     (intr_enable0_qs)
231                       );
232                     
233                     
234                       // Subregister 0 of Multireg intr_state0
235                       // R[intr_state0]: V(False)
236                       prim_subreg #(
237                         .DW      (1),
238                         .SwAccess(prim_subreg_pkg::SwAccessW1C),
239                         .RESVAL  (1'h0),
240                         .Mubi    (1'b0)
241                       ) u_intr_state0 (
242                         .clk_i   (clk_i),
243                         .rst_ni  (rst_ni),
244                     
245                         // from register interface
246                         .we     (intr_state0_we),
247                         .wd     (intr_state0_wd),
248                     
249                         // from internal hardware
250                         .de     (hw2reg.intr_state0[0].de),
251                         .d      (hw2reg.intr_state0[0].d),
252                     
253                         // to internal hardware
254                         .qe     (),
255                         .q      (reg2hw.intr_state0[0].q),
256                         .ds     (),
257                     
258                         // to register interface (read)
259                         .qs     (intr_state0_qs)
260                       );
261                     
262                     
263                       // Subregister 0 of Multireg intr_test0
264                       // R[intr_test0]: V(True)
265                       logic intr_test0_qe;
266                       logic [0:0] intr_test0_flds_we;
267        1/1            assign intr_test0_qe = &intr_test0_flds_we;
           Tests:       T7 T8 T11 
268                       prim_subreg_ext #(
269                         .DW    (1)
270                       ) u_intr_test0 (
271                         .re     (1'b0),
272                         .we     (intr_test0_we),
273                         .wd     (intr_test0_wd),
274                         .d      ('0),
275                         .qre    (),
276                         .qe     (intr_test0_flds_we[0]),
277                         .q      (reg2hw.intr_test0[0].q),
278                         .ds     (),
279                         .qs     ()
280                       );
281        1/1            assign reg2hw.intr_test0[0].qe = intr_test0_qe;
           Tests:       T7 T8 T11 
282                     
283                     
284                       // R[cfg0]: V(False)
285                       //   F[prescale]: 11:0
286                       prim_subreg #(
287                         .DW      (12),
288                         .SwAccess(prim_subreg_pkg::SwAccessRW),
289                         .RESVAL  (12'h0),
290                         .Mubi    (1'b0)
291                       ) u_cfg0_prescale (
292                         .clk_i   (clk_i),
293                         .rst_ni  (rst_ni),
294                     
295                         // from register interface
296                         .we     (cfg0_we),
297                         .wd     (cfg0_prescale_wd),
298                     
299                         // from internal hardware
300                         .de     (1'b0),
301                         .d      ('0),
302                     
303                         // to internal hardware
304                         .qe     (),
305                         .q      (reg2hw.cfg0.prescale.q),
306                         .ds     (),
307                     
308                         // to register interface (read)
309                         .qs     (cfg0_prescale_qs)
310                       );
311                     
312                       //   F[step]: 23:16
313                       prim_subreg #(
314                         .DW      (8),
315                         .SwAccess(prim_subreg_pkg::SwAccessRW),
316                         .RESVAL  (8'h1),
317                         .Mubi    (1'b0)
318                       ) u_cfg0_step (
319                         .clk_i   (clk_i),
320                         .rst_ni  (rst_ni),
321                     
322                         // from register interface
323                         .we     (cfg0_we),
324                         .wd     (cfg0_step_wd),
325                     
326                         // from internal hardware
327                         .de     (1'b0),
328                         .d      ('0),
329                     
330                         // to internal hardware
331                         .qe     (),
332                         .q      (reg2hw.cfg0.step.q),
333                         .ds     (),
334                     
335                         // to register interface (read)
336                         .qs     (cfg0_step_qs)
337                       );
338                     
339                     
340                       // R[timer_v_lower0]: V(False)
341                       prim_subreg #(
342                         .DW      (32),
343                         .SwAccess(prim_subreg_pkg::SwAccessRW),
344                         .RESVAL  (32'h0),
345                         .Mubi    (1'b0)
346                       ) u_timer_v_lower0 (
347                         .clk_i   (clk_i),
348                         .rst_ni  (rst_ni),
349                     
350                         // from register interface
351                         .we     (timer_v_lower0_we),
352                         .wd     (timer_v_lower0_wd),
353                     
354                         // from internal hardware
355                         .de     (hw2reg.timer_v_lower0.de),
356                         .d      (hw2reg.timer_v_lower0.d),
357                     
358                         // to internal hardware
359                         .qe     (),
360                         .q      (reg2hw.timer_v_lower0.q),
361                         .ds     (),
362                     
363                         // to register interface (read)
364                         .qs     (timer_v_lower0_qs)
365                       );
366                     
367                     
368                       // R[timer_v_upper0]: V(False)
369                       prim_subreg #(
370                         .DW      (32),
371                         .SwAccess(prim_subreg_pkg::SwAccessRW),
372                         .RESVAL  (32'h0),
373                         .Mubi    (1'b0)
374                       ) u_timer_v_upper0 (
375                         .clk_i   (clk_i),
376                         .rst_ni  (rst_ni),
377                     
378                         // from register interface
379                         .we     (timer_v_upper0_we),
380                         .wd     (timer_v_upper0_wd),
381                     
382                         // from internal hardware
383                         .de     (hw2reg.timer_v_upper0.de),
384                         .d      (hw2reg.timer_v_upper0.d),
385                     
386                         // to internal hardware
387                         .qe     (),
388                         .q      (reg2hw.timer_v_upper0.q),
389                         .ds     (),
390                     
391                         // to register interface (read)
392                         .qs     (timer_v_upper0_qs)
393                       );
394                     
395                     
396                       // R[compare_lower0_0]: V(False)
397                       logic compare_lower0_0_qe;
398                       logic [0:0] compare_lower0_0_flds_we;
399                       prim_flop #(
400                         .Width(1),
401                         .ResetValue(0)
402                       ) u_compare_lower0_00_qe (
403                         .clk_i(clk_i),
404                         .rst_ni(rst_ni),
405                         .d_i(&compare_lower0_0_flds_we),
406                         .q_o(compare_lower0_0_qe)
407                       );
408                       prim_subreg #(
409                         .DW      (32),
410                         .SwAccess(prim_subreg_pkg::SwAccessRW),
411                         .RESVAL  (32'hffffffff),
412                         .Mubi    (1'b0)
413                       ) u_compare_lower0_0 (
414                         .clk_i   (clk_i),
415                         .rst_ni  (rst_ni),
416                     
417                         // from register interface
418                         .we     (compare_lower0_0_we),
419                         .wd     (compare_lower0_0_wd),
420                     
421                         // from internal hardware
422                         .de     (1'b0),
423                         .d      ('0),
424                     
425                         // to internal hardware
426                         .qe     (compare_lower0_0_flds_we[0]),
427                         .q      (reg2hw.compare_lower0_0.q),
428                         .ds     (),
429                     
430                         // to register interface (read)
431                         .qs     (compare_lower0_0_qs)
432                       );
433        1/1            assign reg2hw.compare_lower0_0.qe = compare_lower0_0_qe;
           Tests:       T1 T2 T3 
434                     
435                     
436                       // R[compare_upper0_0]: V(False)
437                       logic compare_upper0_0_qe;
438                       logic [0:0] compare_upper0_0_flds_we;
439                       prim_flop #(
440                         .Width(1),
441                         .ResetValue(0)
442                       ) u_compare_upper0_00_qe (
443                         .clk_i(clk_i),
444                         .rst_ni(rst_ni),
445                         .d_i(&compare_upper0_0_flds_we),
446                         .q_o(compare_upper0_0_qe)
447                       );
448                       prim_subreg #(
449                         .DW      (32),
450                         .SwAccess(prim_subreg_pkg::SwAccessRW),
451                         .RESVAL  (32'hffffffff),
452                         .Mubi    (1'b0)
453                       ) u_compare_upper0_0 (
454                         .clk_i   (clk_i),
455                         .rst_ni  (rst_ni),
456                     
457                         // from register interface
458                         .we     (compare_upper0_0_we),
459                         .wd     (compare_upper0_0_wd),
460                     
461                         // from internal hardware
462                         .de     (1'b0),
463                         .d      ('0),
464                     
465                         // to internal hardware
466                         .qe     (compare_upper0_0_flds_we[0]),
467                         .q      (reg2hw.compare_upper0_0.q),
468                         .ds     (),
469                     
470                         // to register interface (read)
471                         .qs     (compare_upper0_0_qs)
472                       );
473        1/1            assign reg2hw.compare_upper0_0.qe = compare_upper0_0_qe;
           Tests:       T1 T2 T3 
474                     
475                     
476                     
477                       logic [9:0] addr_hit;
478                       always_comb begin
479        1/1              addr_hit = '0;
           Tests:       T1 T2 T3 
480        1/1              addr_hit[0] = (reg_addr == RV_TIMER_ALERT_TEST_OFFSET);
           Tests:       T1 T2 T3 
481        1/1              addr_hit[1] = (reg_addr == RV_TIMER_CTRL_OFFSET);
           Tests:       T1 T2 T3 
482        1/1              addr_hit[2] = (reg_addr == RV_TIMER_INTR_ENABLE0_OFFSET);
           Tests:       T1 T2 T3 
483        1/1              addr_hit[3] = (reg_addr == RV_TIMER_INTR_STATE0_OFFSET);
           Tests:       T1 T2 T3 
484        1/1              addr_hit[4] = (reg_addr == RV_TIMER_INTR_TEST0_OFFSET);
           Tests:       T1 T2 T3 
485        1/1              addr_hit[5] = (reg_addr == RV_TIMER_CFG0_OFFSET);
           Tests:       T1 T2 T3 
486        1/1              addr_hit[6] = (reg_addr == RV_TIMER_TIMER_V_LOWER0_OFFSET);
           Tests:       T1 T2 T3 
487        1/1              addr_hit[7] = (reg_addr == RV_TIMER_TIMER_V_UPPER0_OFFSET);
           Tests:       T1 T2 T3 
488        1/1              addr_hit[8] = (reg_addr == RV_TIMER_COMPARE_LOWER0_0_OFFSET);
           Tests:       T1 T2 T3 
489        1/1              addr_hit[9] = (reg_addr == RV_TIMER_COMPARE_UPPER0_0_OFFSET);
           Tests:       T1 T2 T3 
490                       end
491                     
492        1/1            assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
           Tests:       T1 T2 T3 
493                     
494                       // Check sub-word write is permitted
495                       always_comb begin
496        1/1              wr_err = (reg_we &
           Tests:       T1 T2 T3 
497                                   ((addr_hit[0] & (|(RV_TIMER_PERMIT[0] & ~reg_be))) |
498                                    (addr_hit[1] & (|(RV_TIMER_PERMIT[1] & ~reg_be))) |
499                                    (addr_hit[2] & (|(RV_TIMER_PERMIT[2] & ~reg_be))) |
500                                    (addr_hit[3] & (|(RV_TIMER_PERMIT[3] & ~reg_be))) |
501                                    (addr_hit[4] & (|(RV_TIMER_PERMIT[4] & ~reg_be))) |
502                                    (addr_hit[5] & (|(RV_TIMER_PERMIT[5] & ~reg_be))) |
503                                    (addr_hit[6] & (|(RV_TIMER_PERMIT[6] & ~reg_be))) |
504                                    (addr_hit[7] & (|(RV_TIMER_PERMIT[7] & ~reg_be))) |
505                                    (addr_hit[8] & (|(RV_TIMER_PERMIT[8] & ~reg_be))) |
506                                    (addr_hit[9] & (|(RV_TIMER_PERMIT[9] & ~reg_be)))));
507                       end
508                     
509                       // Generate write-enables
510        1/1            assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
           Tests:       T2 T3 T4 
511                     
512        1/1            assign alert_test_wd = reg_wdata[0];
           Tests:       T1 T2 T3 
513        1/1            assign ctrl_we = addr_hit[1] & reg_we & !reg_error;
           Tests:       T2 T3 T4 
514                     
515        1/1            assign ctrl_wd = reg_wdata[0];
           Tests:       T1 T2 T3 
516        1/1            assign intr_enable0_we = addr_hit[2] & reg_we & !reg_error;
           Tests:       T2 T3 T4 
517                     
518        1/1            assign intr_enable0_wd = reg_wdata[0];
           Tests:       T1 T2 T3 
519        1/1            assign intr_state0_we = addr_hit[3] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
520                     
521        1/1            assign intr_state0_wd = reg_wdata[0];
           Tests:       T1 T2 T3 
522        1/1            assign intr_test0_we = addr_hit[4] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
523                     
524        1/1            assign intr_test0_wd = reg_wdata[0];
           Tests:       T1 T2 T3 
525        1/1            assign cfg0_we = addr_hit[5] & reg_we & !reg_error;
           Tests:       T2 T3 T4 
526                     
527        1/1            assign cfg0_prescale_wd = reg_wdata[11:0];
           Tests:       T1 T2 T3 
528                     
529        1/1            assign cfg0_step_wd = reg_wdata[23:16];
           Tests:       T1 T2 T3 
530        1/1            assign timer_v_lower0_we = addr_hit[6] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
531                     
532        1/1            assign timer_v_lower0_wd = reg_wdata[31:0];
           Tests:       T1 T2 T3 
533        1/1            assign timer_v_upper0_we = addr_hit[7] & reg_we & !reg_error;
           Tests:       T2 T3 T4 
534                     
535        1/1            assign timer_v_upper0_wd = reg_wdata[31:0];
           Tests:       T1 T2 T3 
536        1/1            assign compare_lower0_0_we = addr_hit[8] & reg_we & !reg_error;
           Tests:       T2 T3 T4 
537                     
538        1/1            assign compare_lower0_0_wd = reg_wdata[31:0];
           Tests:       T1 T2 T3 
539        1/1            assign compare_upper0_0_we = addr_hit[9] & reg_we & !reg_error;
           Tests:       T2 T3 T4 
540                     
541        1/1            assign compare_upper0_0_wd = reg_wdata[31:0];
           Tests:       T1 T2 T3 
542                     
543                       // Assign write-enables to checker logic vector.
544                       always_comb begin
545        1/1              reg_we_check = '0;
           Tests:       T6 T7 T8 
546        1/1              reg_we_check[0] = alert_test_we;
           Tests:       T6 T7 T8 
547        1/1              reg_we_check[1] = ctrl_we;
           Tests:       T6 T7 T8 
548        1/1              reg_we_check[2] = intr_enable0_we;
           Tests:       T6 T7 T8 
549        1/1              reg_we_check[3] = intr_state0_we;
           Tests:       T6 T7 T8 
550        1/1              reg_we_check[4] = intr_test0_we;
           Tests:       T6 T7 T8 
551        1/1              reg_we_check[5] = cfg0_we;
           Tests:       T6 T7 T8 
552        1/1              reg_we_check[6] = timer_v_lower0_we;
           Tests:       T6 T7 T8 
553        1/1              reg_we_check[7] = timer_v_upper0_we;
           Tests:       T6 T7 T8 
554        1/1              reg_we_check[8] = compare_lower0_0_we;
           Tests:       T6 T7 T8 
555        1/1              reg_we_check[9] = compare_upper0_0_we;
           Tests:       T6 T7 T8 
556                       end
557                     
558                       // Read data return
559                       always_comb begin
560        1/1              reg_rdata_next = '0;
           Tests:       T1 T2 T3 
561        1/1              unique case (1'b1)
           Tests:       T1 T2 T3 
562                           addr_hit[0]: begin
563        1/1                  reg_rdata_next[0] = '0;
           Tests:       T2 T3 T4 
564                           end
565                     
566                           addr_hit[1]: begin
567        1/1                  reg_rdata_next[0] = ctrl_qs;
           Tests:       T2 T3 T4 
568                           end
569                     
570                           addr_hit[2]: begin
571        1/1                  reg_rdata_next[0] = intr_enable0_qs;
           Tests:       T2 T3 T4 
572                           end
573                     
574                           addr_hit[3]: begin
575        1/1                  reg_rdata_next[0] = intr_state0_qs;
           Tests:       T1 T2 T3 
576                           end
577                     
578                           addr_hit[4]: begin
579        1/1                  reg_rdata_next[0] = '0;
           Tests:       T1 T2 T3 
580                           end
581                     
582                           addr_hit[5]: begin
583        1/1                  reg_rdata_next[11:0] = cfg0_prescale_qs;
           Tests:       T2 T3 T4 
584        1/1                  reg_rdata_next[23:16] = cfg0_step_qs;
           Tests:       T2 T3 T4 
585                           end
586                     
587                           addr_hit[6]: begin
588        1/1                  reg_rdata_next[31:0] = timer_v_lower0_qs;
           Tests:       T2 T3 T4 
589                           end
590                     
591                           addr_hit[7]: begin
592        1/1                  reg_rdata_next[31:0] = timer_v_upper0_qs;
           Tests:       T2 T3 T4 
593                           end
594                     
595                           addr_hit[8]: begin
596        1/1                  reg_rdata_next[31:0] = compare_lower0_0_qs;
           Tests:       T2 T3 T4 
597                           end
598                     
599                           addr_hit[9]: begin
600        1/1                  reg_rdata_next[31:0] = compare_upper0_0_qs;
           Tests:       T2 T3 T4 
601                           end
602                     
603                           default: begin
604                             reg_rdata_next = '1;
605                           end
606                         endcase
607                       end
608                     
609                       // shadow busy
610                       logic shadow_busy;
611                       assign shadow_busy = 1'b0;
612                     
613                       // register busy
614        unreachable    assign reg_busy = shadow_busy;
615                     
616                       // Unused signal tieoff
617                     
618                       // wdata / byte enable are not always fully used
619                       // add a blanket unused statement to handle lint waivers
620                       logic unused_wdata;
621                       logic unused_be;
622        1/1            assign unused_wdata = ^reg_wdata;
           Tests:       T1 T2 T3 
623        1/1            assign unused_be = ^reg_be;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rv_timer_reg_top

	Total	Covered	Percent
Conditions	123	123	100.00
Logical	123	123	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T13
1	1	Covered	T6,T7,T8

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T16,T17

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T15,T16,T17
1	0	0	Covered	T1,T2,T3

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T15,T16,T17
0	1	0	Covered	T7,T8,T13
1	0	0	Covered	T7,T8,T13

 LINE       480
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T11

 LINE       481
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_CTRL_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       482
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_INTR_ENABLE0_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       483
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_INTR_STATE0_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       484
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_INTR_TEST0_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T8

 LINE       485
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_CFG0_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       486
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_TIMER_V_LOWER0_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       487
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_TIMER_V_UPPER0_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       488
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_COMPARE_LOWER0_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       489
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_COMPARE_UPPER0_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       492
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       492
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       496
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T6,T7,T8
1	1	Covered	T7,T8,T13

 LINE       496
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T5
0	0	0	0	0	0	0	0	0	1	Covered	T7,T8,T14
0	0	0	0	0	0	0	0	1	0	Covered	T7,T8,T14
0	0	0	0	0	0	0	1	0	0	Covered	T7,T8,T14
0	0	0	0	0	0	1	0	0	0	Covered	T7,T8,T14
0	0	0	0	0	1	0	0	0	0	Covered	T7,T8,T14
0	0	0	0	1	0	0	0	0	0	Covered	T1,T7,T8
0	0	0	1	0	0	0	0	0	0	Covered	T3,T4,T6
0	0	1	0	0	0	0	0	0	0	Covered	T7,T8,T11
0	1	0	0	0	0	0	0	0	0	Covered	T7,T8,T14
1	0	0	0	0	0	0	0	0	0	Covered	T7,T8,T14

 LINE       496
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T7,T8,T11
1	1	Covered	T7,T8,T14

 LINE       496
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T6,T7,T8
1	1	Covered	T7,T8,T14

 LINE       496
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T6,T7,T8
1	1	Covered	T7,T8,T11

 LINE       496
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T5
1	1	Covered	T3,T4,T6

 LINE       496
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T7,T8,T11
1	1	Covered	T1,T7,T8

 LINE       496
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T7,T8,T14

 LINE       496
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T7,T8,T14

 LINE       496
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T7,T8,T14

 LINE       496
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T7,T8,T14

 LINE       496
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T7,T8,T14

 LINE       510
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T7,T8,T11
1	1	0	Covered	T7,T8,T13
1	1	1	Covered	T18,T19,T20

 LINE       513
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T7,T8,T13
1	1	1	Covered	T6,T7,T8

 LINE       516
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T7,T8,T13
1	1	1	Covered	T6,T7,T8

 LINE       519
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T7,T8,T13
1	1	1	Covered	T6,T8,T9

 LINE       522
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T1,T7,T8
1	1	0	Covered	T7,T8,T13
1	1	1	Covered	T8,T11,T13

 LINE       525
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T7,T8,T13
1	1	1	Covered	T6,T7,T8

 LINE       530
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T7,T8,T13
1	1	1	Covered	T6,T7,T8

 LINE       533
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T7,T8,T13
1	1	1	Covered	T6,T7,T8

 LINE       536
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T7,T8,T13
1	1	1	Covered	T6,T7,T8

 LINE       539
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T8
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T7,T8,T13
1	1	1	Covered	T6,T7,T8

---

Branch Coverage for Module : rv_timer_reg_top

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
TERNARY	492	2	2	100.00
IF	68	3	3	100.00
CASE	561	11	11	100.00

492          assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

68             if (!rst_ni) begin
               -1-  
69               err_q <= '0;
                 ==>
70             end else if (intg_err || reg_we_err) begin
                        -2-  
71               err_q <= 1'b1;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

561            unique case (1'b1)
                      -1-  
562              addr_hit[0]: begin
563                reg_rdata_next[0] = '0;
                   ==>
564              end
565        
566              addr_hit[1]: begin
567                reg_rdata_next[0] = ctrl_qs;
                   ==>
568              end
569        
570              addr_hit[2]: begin
571                reg_rdata_next[0] = intr_enable0_qs;
                   ==>
572              end
573        
574              addr_hit[3]: begin
575                reg_rdata_next[0] = intr_state0_qs;
                   ==>
576              end
577        
578              addr_hit[4]: begin
579                reg_rdata_next[0] = '0;
                   ==>
580              end
581        
582              addr_hit[5]: begin
583                reg_rdata_next[11:0] = cfg0_prescale_qs;
                   ==>
584                reg_rdata_next[23:16] = cfg0_step_qs;
585              end
586        
587              addr_hit[6]: begin
588                reg_rdata_next[31:0] = timer_v_lower0_qs;
                   ==>
589              end
590        
591              addr_hit[7]: begin
592                reg_rdata_next[31:0] = timer_v_upper0_qs;
                   ==>
593              end
594        
595              addr_hit[8]: begin
596                reg_rdata_next[31:0] = compare_lower0_0_qs;
                   ==>
597              end
598        
599              addr_hit[9]: begin
600                reg_rdata_next[31:0] = compare_upper0_0_qs;
                   ==>
601              end
602        
603              default: begin
604                reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T2,T3,T4
addr_hit[1]	Covered	T2,T3,T4
addr_hit[2]	Covered	T2,T3,T4
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T2,T3,T4
addr_hit[6]	Covered	T2,T3,T4
addr_hit[7]	Covered	T2,T3,T4
addr_hit[8]	Covered	T2,T3,T4
addr_hit[9]	Covered	T2,T3,T4
default	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_timer_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	136761012	0	0
reAfterRv	2147483647	136761002	0	0
rePulse	2147483647	136719299	0	0
wePulse	2147483647	41703	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	136761012	0	0
T1	6989	1	0	0
T2	7866	1	0	0
T3	11254	1	0	0
T4	11670	1	0	0
T5	7271	1	0	0
T6	102559	3261	0	0
T7	118708	544	0	0
T8	299404	1528	0	0
T9	25231	614	0	0
T10	332725	27990	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	136761002	0	0
T1	6989	1	0	0
T2	7866	1	0	0
T3	11254	1	0	0
T4	11670	1	0	0
T5	7271	1	0	0
T6	102559	3260	0	0
T7	118708	544	0	0
T8	299404	1528	0	0
T9	25231	614	0	0
T10	332725	27989	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	136719299	0	0
T1	6989	1	0	0
T2	7866	1	0	0
T3	11254	1	0	0
T4	11670	1	0	0
T5	7271	1	0	0
T6	102559	3221	0	0
T7	118708	310	0	0
T8	299404	919	0	0
T9	25231	567	0	0
T10	332725	27939	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41703	0	0
T6	102559	39	0	0
T7	118708	234	0	0
T8	299404	609	0	0
T9	25231	47	0	0
T10	332725	50	0	0
T11	1240	10	0	0
T12	592785	62	0	0
T14	231765	10	0	0
T21	12701	30	0	0
T22	414004	39	0	0