Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	144437	0	0
cfg0_rd_A	2147483647	3002	0	0
compare_lower0_0_rd_A	2147483647	2911	0	0
compare_upper0_0_rd_A	2147483647	2703	0	0
ctrl_rd_A	2147483647	2723	0	0
intr_enable0_rd_A	2147483647	3900	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	144437	0	0
T7	118708	6290	0	0
T8	299404	14033	0	0
T9	25231	0	0	0
T10	332725	0	0	0
T11	1240	0	0	0
T12	592785	0	0	0
T13	0	3126	0	0
T14	231765	0	0	0
T21	12701	0	0	0
T22	414004	0	0	0
T23	0	301	0	0
T24	0	11968	0	0
T25	0	6367	0	0
T26	0	12431	0	0
T27	0	9515	0	0
T28	0	3884	0	0
T29	0	5980	0	0
T30	149762	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3002	0	0
T15	0	39	0	0
T19	0	11	0	0
T23	14295	16	0	0
T24	0	114	0	0
T25	0	36	0	0
T26	0	174	0	0
T29	0	103	0	0
T31	0	26	0	0
T32	0	15	0	0
T33	0	15	0	0
T34	818159	0	0	0
T35	269362	0	0	0
T36	128309	0	0	0
T37	570156	0	0	0
T38	1132	0	0	0
T39	322273	0	0	0
T40	160859	0	0	0
T41	487447	0	0	0
T42	157556	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2911	0	0
T15	0	47	0	0
T19	0	9	0	0
T23	14295	28	0	0
T24	0	148	0	0
T25	0	11	0	0
T26	0	181	0	0
T29	0	87	0	0
T31	0	9	0	0
T32	0	6	0	0
T33	0	6	0	0
T34	818159	0	0	0
T35	269362	0	0	0
T36	128309	0	0	0
T37	570156	0	0	0
T38	1132	0	0	0
T39	322273	0	0	0
T40	160859	0	0	0
T41	487447	0	0	0
T42	157556	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2703	0	0
T15	0	51	0	0
T19	0	5	0	0
T23	14295	22	0	0
T24	0	129	0	0
T25	0	71	0	0
T26	0	164	0	0
T29	0	86	0	0
T31	0	13	0	0
T32	0	17	0	0
T34	818159	0	0	0
T35	269362	0	0	0
T36	128309	0	0	0
T37	570156	0	0	0
T38	1132	0	0	0
T39	322273	0	0	0
T40	160859	0	0	0
T41	487447	0	0	0
T42	157556	0	0	0
T43	0	4	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2723	0	0
T15	0	27	0	0
T19	0	4	0	0
T23	14295	3	0	0
T24	0	65	0	0
T25	0	43	0	0
T26	0	196	0	0
T29	0	101	0	0
T31	0	18	0	0
T32	0	14	0	0
T34	818159	0	0	0
T35	269362	0	0	0
T36	128309	0	0	0
T37	570156	0	0	0
T38	1132	0	0	0
T39	322273	0	0	0
T40	160859	0	0	0
T41	487447	0	0	0
T42	157556	0	0	0
T43	0	15	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3900	0	0
T23	0	26	0	0
T24	0	256	0	0
T25	0	114	0	0
T26	0	258	0	0
T29	0	108	0	0
T44	560771	24	0	0
T45	0	37	0	0
T46	0	21	0	0
T47	0	22	0	0
T48	0	14	0	0
T49	11909	0	0	0
T50	426411	0	0	0
T51	992298	0	0	0
T52	553451	0	0	0
T53	769610	0	0	0
T54	454772	0	0	0
T55	797805	0	0	0
T56	640492	0	0	0
T57	948226	0	0	0