Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59488141	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59609437

1

T1

10

T2

235

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	118974160	1			T1	8		T2	444		T3	1
values[0x0]	59209	1			T1	2		T2	14		T8	11
values[0x1]	64209	1			T1	8		T2	15		T8	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47538285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

71559293

1

T1

13

T2

275

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	361415	1			T2	5		T9	80		T14	14
valid_sources[0x01]	393622	1			T2	2		T9	93		T14	27
valid_sources[0x02]	357232	1			T2	3		T9	96		T14	18
valid_sources[0x03]	394110	1			T9	100		T14	35		T11	36
valid_sources[0x04]	359509	1			T2	4		T9	98		T10	1
valid_sources[0x05]	360090	1			T2	1		T9	94		T10	2
valid_sources[0x06]	545799	1			T2	2		T9	91		T10	1
valid_sources[0x07]	366860	1			T9	88		T10	1		T18	1
valid_sources[0x08]	360366	1			T2	3		T9	108		T14	27
valid_sources[0x09]	359673	1			T2	2		T9	96		T10	1
valid_sources[0x0a]	358448	1			T9	97		T10	7		T18	1
valid_sources[0x0b]	359728	1			T2	1		T9	101		T10	1
valid_sources[0x0c]	357354	1			T2	1		T9	107		T10	1
valid_sources[0x0d]	360368	1			T2	1		T9	91		T10	2
valid_sources[0x0e]	360603	1			T9	78		T14	9		T11	21
valid_sources[0x0f]	357981	1			T1	1		T2	3		T9	88
valid_sources[0x10]	360395	1			T9	102		T14	23		T11	15
valid_sources[0x11]	360521	1			T2	4		T9	117		T10	3
valid_sources[0x12]	509156	1			T2	4		T9	90		T10	2
valid_sources[0x13]	361615	1			T2	3		T9	89		T10	1
valid_sources[0x14]	654470	1			T2	2		T9	86		T14	26
valid_sources[0x15]	360292	1			T2	5		T9	105		T10	1
valid_sources[0x16]	1260653	1			T9	79		T14	17		T11	48
valid_sources[0x17]	361448	1			T2	1		T9	103		T10	3
valid_sources[0x18]	362994	1			T2	2		T9	108		T10	1
valid_sources[0x19]	744146	1			T2	4		T9	101		T10	3
valid_sources[0x1a]	360242	1			T2	4		T4	1		T9	89
valid_sources[0x1b]	359745	1			T2	1		T9	109		T10	1
valid_sources[0x1c]	370697	1			T2	3		T9	82		T10	6
valid_sources[0x1d]	359181	1			T9	93		T10	1		T14	28
valid_sources[0x1e]	358780	1			T2	2		T9	110		T10	2
valid_sources[0x1f]	358539	1			T2	2		T9	91		T14	10
valid_sources[0x20]	3865836	1			T2	1		T9	97		T14	22
valid_sources[0x21]	432457	1			T2	7		T9	89		T10	2
valid_sources[0x22]	359571	1			T9	98		T10	2		T14	20
valid_sources[0x23]	359955	1			T2	1		T9	96		T10	1
valid_sources[0x24]	360390	1			T2	4		T9	89		T10	2
valid_sources[0x25]	2089449	1			T2	1		T9	92		T17	5
valid_sources[0x26]	359009	1			T2	2		T9	108		T10	1
valid_sources[0x27]	359967	1			T2	1		T9	107		T10	1
valid_sources[0x28]	359569	1			T2	2		T9	106		T14	25
valid_sources[0x29]	361261	1			T2	5		T9	116		T14	17
valid_sources[0x2a]	359338	1			T2	4		T9	111		T14	16
valid_sources[0x2b]	358698	1			T2	2		T9	101		T14	35
valid_sources[0x2c]	360711	1			T9	97		T14	12		T11	23
valid_sources[0x2d]	357794	1			T2	2		T9	93		T10	1
valid_sources[0x2e]	414672	1			T2	2		T9	93		T14	23
valid_sources[0x2f]	358929	1			T2	2		T9	94		T18	1
valid_sources[0x30]	1406578	1			T9	83		T14	21		T11	35
valid_sources[0x31]	362262	1			T2	2		T9	105		T14	21
valid_sources[0x32]	1074968	1			T2	1		T9	108		T14	11
valid_sources[0x33]	363366	1			T2	4		T9	94		T10	1
valid_sources[0x34]	358173	1			T2	1		T9	84		T10	2
valid_sources[0x35]	363898	1			T2	2		T9	87		T14	25
valid_sources[0x36]	360410	1			T2	1		T9	96		T18	1
valid_sources[0x37]	367524	1			T9	99		T10	1		T14	20
valid_sources[0x38]	361170	1			T2	4		T9	110		T10	3
valid_sources[0x39]	362058	1			T2	4		T9	85		T10	1
valid_sources[0x3a]	360686	1			T2	1		T9	107		T14	27
valid_sources[0x3b]	361907	1			T2	1		T9	112		T14	24
valid_sources[0x3c]	763403	1			T2	2		T9	99		T10	2
valid_sources[0x3d]	357044	1			T2	1		T9	115		T10	2
valid_sources[0x3e]	417323	1			T2	3		T9	87		T14	13
valid_sources[0x3f]	359491	1			T2	1		T9	104		T14	18
valid_sources[0x40]	434191	1			T2	3		T9	96		T14	14
valid_sources[0x41]	436128	1			T9	102		T10	4		T14	20
valid_sources[0x42]	359608	1			T9	87		T10	4		T14	22
valid_sources[0x43]	359681	1			T2	3		T9	107		T10	2
valid_sources[0x44]	359280	1			T2	4		T9	90		T14	26
valid_sources[0x45]	359220	1			T2	4		T9	129		T14	34
valid_sources[0x46]	357434	1			T2	3		T9	92		T10	3
valid_sources[0x47]	360842	1			T2	1		T9	76		T14	14
valid_sources[0x48]	360913	1			T2	1		T9	101		T10	2
valid_sources[0x49]	358492	1			T2	1		T9	99		T14	14
valid_sources[0x4a]	1068997	1			T2	2		T9	118		T10	2
valid_sources[0x4b]	357878	1			T2	2		T9	95		T17	1
valid_sources[0x4c]	538431	1			T9	85		T14	21		T11	28
valid_sources[0x4d]	358509	1			T2	2		T9	97		T14	16
valid_sources[0x4e]	360947	1			T2	4		T9	95		T10	1
valid_sources[0x4f]	360155	1			T1	1		T2	1		T9	92
valid_sources[0x50]	358268	1			T2	6		T9	100		T14	23
valid_sources[0x51]	359540	1			T2	6		T9	84		T10	1
valid_sources[0x52]	436701	1			T9	92		T10	1		T14	17
valid_sources[0x53]	358086	1			T2	1		T9	93		T10	1
valid_sources[0x54]	363508	1			T2	2		T9	105		T10	1
valid_sources[0x55]	946392	1			T2	3		T9	89		T14	12
valid_sources[0x56]	357531	1			T2	5		T9	110		T14	14
valid_sources[0x57]	358633	1			T1	1		T9	97		T14	12
valid_sources[0x58]	359969	1			T2	1		T9	98		T14	24
valid_sources[0x59]	358713	1			T2	2		T9	87		T14	20
valid_sources[0x5a]	358734	1			T2	2		T9	101		T14	18
valid_sources[0x5b]	365117	1			T2	4		T9	111		T10	1
valid_sources[0x5c]	357660	1			T2	4		T9	122		T14	12
valid_sources[0x5d]	697620	1			T2	2		T9	94		T10	2
valid_sources[0x5e]	360276	1			T9	110		T10	2		T14	10
valid_sources[0x5f]	359175	1			T2	1		T9	101		T14	8
valid_sources[0x60]	358796	1			T9	90		T14	35		T11	13
valid_sources[0x61]	360096	1			T9	87		T14	20		T11	15
valid_sources[0x62]	1014921	1			T2	3		T9	91		T14	13
valid_sources[0x63]	360138	1			T2	2		T9	102		T14	40
valid_sources[0x64]	371145	1			T2	4		T9	94		T10	1
valid_sources[0x65]	517720	1			T2	1		T9	110		T14	25
valid_sources[0x66]	360239	1			T9	106		T10	1		T14	23
valid_sources[0x67]	357707	1			T2	3		T9	112		T14	19
valid_sources[0x68]	394021	1			T2	1		T9	111		T10	2
valid_sources[0x69]	362495	1			T2	2		T9	106		T10	4
valid_sources[0x6a]	359874	1			T2	5		T9	75		T10	1
valid_sources[0x6b]	362997	1			T2	2		T9	85		T10	2
valid_sources[0x6c]	361890	1			T2	3		T9	92		T10	1
valid_sources[0x6d]	356358	1			T2	5		T9	95		T10	2
valid_sources[0x6e]	359358	1			T6	1		T9	94		T10	1
valid_sources[0x6f]	1037764	1			T2	2		T9	94		T10	1
valid_sources[0x70]	360917	1			T9	75		T10	1		T14	13
valid_sources[0x71]	362558	1			T9	87		T14	14		T11	20
valid_sources[0x72]	360448	1			T2	2		T9	91		T10	1
valid_sources[0x73]	360925	1			T2	4		T9	102		T10	1
valid_sources[0x74]	381782	1			T9	89		T14	11		T11	28
valid_sources[0x75]	358480	1			T2	2		T9	104		T10	1
valid_sources[0x76]	670987	1			T9	94		T14	18		T11	30
valid_sources[0x77]	905659	1			T2	2		T9	112		T10	1
valid_sources[0x78]	360075	1			T2	1		T9	98		T10	1
valid_sources[0x79]	361234	1			T2	2		T9	104		T14	21
valid_sources[0x7a]	356214	1			T2	2		T9	97		T14	31
valid_sources[0x7b]	424389	1			T2	1		T9	104		T10	2
valid_sources[0x7c]	358547	1			T9	100		T10	1		T14	28
valid_sources[0x7d]	362571	1			T2	3		T9	88		T10	3
valid_sources[0x7e]	361589	1			T9	95		T18	1		T14	21
valid_sources[0x7f]	359789	1			T2	1		T9	96		T14	25
valid_sources[0x80]	356321	1			T2	2		T9	81		T14	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59503206

1

T1

3

T2

216

T3

1

values[0x0]

all_enables

biggest_size

53657

1

T1

2

T2

8

T8

8

values[0x1]

all_enables

biggest_size

52574

1

T1

5

T2

11

T8

8