Unified Coverage Report :: Module

Module : prim_intr_hw

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_harts[0].u_intr_hw	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.gen_harts[0].u_intr_hw

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_intr_hw

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Module : prim_intr_hw

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T14,T15
1	0	Covered	T11,T12,T13

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T14,T15

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T14,T15,T11
1	1	Covered	T10,T15,T11

Branch Coverage for Module : prim_intr_hw

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : prim_intr_hw

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	413	413	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	413	413
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1