Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	136213	0	0
cfg0_rd_A	2147483647	2009	0	0
compare_lower0_0_rd_A	2147483647	2069	0	0
compare_upper0_0_rd_A	2147483647	1991	0	0
ctrl_rd_A	2147483647	1888	0	0
intr_enable0_rd_A	2147483647	2960	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	136213	0	0
T11	214299	6459	0	0
T12	0	7644	0	0
T13	0	10952	0	0
T16	126257	0	0	0
T24	0	16840	0	0
T25	0	17578	0	0
T26	0	10266	0	0
T27	0	3729	0	0
T28	0	5824	0	0
T29	0	10708	0	0
T30	0	16359	0	0
T31	695646	0	0	0
T32	179322	0	0	0
T33	390475	0	0	0
T34	616757	0	0	0
T35	74715	0	0	0
T36	520519	0	0	0
T37	140172	0	0	0
T38	426764	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2009	0	0
T21	0	60	0	0
T22	0	5	0	0
T23	0	17	0	0
T25	682271	245	0	0
T26	224586	0	0	0
T39	0	89	0	0
T40	0	4	0	0
T41	0	436	0	0
T42	0	56	0	0
T43	0	437	0	0
T44	0	1	0	0
T45	920930	0	0	0
T46	116730	0	0	0
T47	139946	0	0	0
T48	345175	0	0	0
T49	810825	0	0	0
T50	244695	0	0	0
T51	734177	0	0	0
T52	112464	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2069	0	0
T21	0	42	0	0
T22	0	3	0	0
T23	0	7	0	0
T25	682271	278	0	0
T26	224586	0	0	0
T39	0	82	0	0
T40	0	5	0	0
T41	0	486	0	0
T42	0	22	0	0
T43	0	482	0	0
T44	0	8	0	0
T45	920930	0	0	0
T46	116730	0	0	0
T47	139946	0	0	0
T48	345175	0	0	0
T49	810825	0	0	0
T50	244695	0	0	0
T51	734177	0	0	0
T52	112464	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1991	0	0
T21	0	29	0	0
T22	0	3	0	0
T25	682271	202	0	0
T26	224586	0	0	0
T39	0	88	0	0
T41	0	496	0	0
T42	0	36	0	0
T43	0	485	0	0
T44	0	7	0	0
T45	920930	0	0	0
T46	116730	0	0	0
T47	139946	0	0	0
T48	345175	0	0	0
T49	810825	0	0	0
T50	244695	0	0	0
T51	734177	0	0	0
T52	112464	0	0	0
T53	0	65	0	0
T54	0	9	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1888	0	0
T21	0	26	0	0
T22	0	3	0	0
T23	0	6	0	0
T25	682271	240	0	0
T26	224586	0	0	0
T39	0	87	0	0
T40	0	7	0	0
T41	0	433	0	0
T42	0	32	0	0
T43	0	483	0	0
T44	0	9	0	0
T45	920930	0	0	0
T46	116730	0	0	0
T47	139946	0	0	0
T48	345175	0	0	0
T49	810825	0	0	0
T50	244695	0	0	0
T51	734177	0	0	0
T52	112464	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2960	0	0
T25	682271	345	0	0
T26	224586	0	0	0
T45	920930	0	0	0
T46	116730	0	0	0
T47	139946	0	0	0
T48	345175	0	0	0
T49	810825	0	0	0
T50	244695	0	0	0
T51	734177	0	0	0
T52	112464	0	0	0
T55	0	69	0	0
T56	0	55	0	0
T57	0	20	0	0
T58	0	2	0	0
T59	0	32	0	0
T60	0	149	0	0
T61	0	24	0	0
T62	0	4	0	0
T63	0	56	0	0