Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	68433715	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

68592570

1

T2

1

T4

189

T5

8515

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136889235	1			T1	1		T2	1		T3	1
values[0x0]	65719	1			T4	4		T5	3084		T6	2
values[0x1]	71331	1			T4	2		T5	3522		T6	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54684406	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

82341879

1

T1

1

T2

1

T4

233

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	427119	1			T4	4		T5	43		T8	46
valid_sources[0x01]	414647	1			T4	4		T5	30		T6	8
valid_sources[0x02]	3754735	1			T5	51		T6	3		T8	13
valid_sources[0x03]	1879654	1			T4	4		T5	62		T8	61
valid_sources[0x04]	413908	1			T5	33		T6	3		T8	21
valid_sources[0x05]	412053	1			T4	5		T5	52		T6	3
valid_sources[0x06]	1065451	1			T4	1		T5	36		T6	8
valid_sources[0x07]	650622	1			T4	3		T5	36		T6	7
valid_sources[0x08]	414519	1			T5	35		T6	1		T8	13
valid_sources[0x09]	904165	1			T4	3		T5	38		T6	5
valid_sources[0x0a]	413338	1			T4	3		T5	35		T6	10
valid_sources[0x0b]	416313	1			T4	3		T5	31		T8	5
valid_sources[0x0c]	414655	1			T5	45		T8	26		T10	66
valid_sources[0x0d]	501025	1			T4	1		T5	39		T6	11
valid_sources[0x0e]	413584	1			T4	4		T5	48		T6	2
valid_sources[0x0f]	412579	1			T4	3		T5	42		T6	5
valid_sources[0x10]	412335	1			T4	4		T5	39		T6	10
valid_sources[0x11]	412734	1			T4	1		T5	28		T6	9
valid_sources[0x12]	417118	1			T4	2		T5	23		T8	23
valid_sources[0x13]	415091	1			T5	40		T6	1		T8	34
valid_sources[0x14]	604677	1			T5	43		T6	5		T7	13
valid_sources[0x15]	414528	1			T4	2		T5	45		T6	2
valid_sources[0x16]	719211	1			T4	2		T5	42		T6	7
valid_sources[0x17]	417157	1			T4	2		T5	36		T6	3
valid_sources[0x18]	414377	1			T4	2		T5	37		T6	3
valid_sources[0x19]	423772	1			T4	3		T5	43		T6	1
valid_sources[0x1a]	418384	1			T4	2		T5	34		T6	2
valid_sources[0x1b]	524635	1			T5	36		T6	1		T7	226
valid_sources[0x1c]	414632	1			T4	1		T5	33		T8	26
valid_sources[0x1d]	868014	1			T4	2		T5	36		T7	1
valid_sources[0x1e]	416173	1			T4	1		T5	38		T6	4
valid_sources[0x1f]	413071	1			T4	1		T5	30		T6	6
valid_sources[0x20]	417942	1			T4	4		T5	46		T6	1
valid_sources[0x21]	416099	1			T4	5		T5	36		T6	5
valid_sources[0x22]	417700	1			T5	35		T6	3		T7	180
valid_sources[0x23]	414839	1			T4	2		T5	26		T6	23
valid_sources[0x24]	418344	1			T4	2		T5	32		T6	1
valid_sources[0x25]	606026	1			T5	42		T6	3		T8	41
valid_sources[0x26]	413058	1			T4	4		T5	55		T8	28
valid_sources[0x27]	414940	1			T4	3		T5	23		T6	5
valid_sources[0x28]	413493	1			T4	1		T5	27		T6	5
valid_sources[0x29]	410776	1			T4	1		T5	53		T6	13
valid_sources[0x2a]	999325	1			T4	2		T5	24		T8	12
valid_sources[0x2b]	413540	1			T4	1		T5	15		T8	25
valid_sources[0x2c]	2529259	1			T4	2		T5	38		T6	3
valid_sources[0x2d]	415196	1			T4	2		T5	25		T7	1
valid_sources[0x2e]	412325	1			T4	1		T5	37		T6	4
valid_sources[0x2f]	413179	1			T4	3		T5	39		T6	4
valid_sources[0x30]	415176	1			T4	1		T5	47		T6	5
valid_sources[0x31]	412856	1			T4	2		T5	35		T6	1
valid_sources[0x32]	411715	1			T5	31		T6	3		T8	33
valid_sources[0x33]	415713	1			T4	3		T5	29		T6	2
valid_sources[0x34]	413649	1			T4	4		T5	35		T6	2
valid_sources[0x35]	410501	1			T4	2		T5	44		T6	6
valid_sources[0x36]	413517	1			T4	3		T5	35		T6	18
valid_sources[0x37]	598538	1			T5	23		T6	15		T8	21
valid_sources[0x38]	412950	1			T4	3		T5	35		T6	4
valid_sources[0x39]	432136	1			T4	3		T5	26		T8	13
valid_sources[0x3a]	413677	1			T4	3		T5	37		T6	3
valid_sources[0x3b]	416201	1			T5	37		T6	5		T7	1
valid_sources[0x3c]	411512	1			T4	2		T5	35		T6	1
valid_sources[0x3d]	418477	1			T4	1		T5	33		T8	11
valid_sources[0x3e]	933515	1			T4	1		T5	24		T6	2
valid_sources[0x3f]	412166	1			T5	39		T6	4		T8	49
valid_sources[0x40]	411523	1			T4	4		T5	45		T6	7
valid_sources[0x41]	415418	1			T5	38		T6	8		T8	29
valid_sources[0x42]	413355	1			T5	55		T8	10		T10	66
valid_sources[0x43]	414484	1			T1	1		T5	34		T6	1
valid_sources[0x44]	413337	1			T4	3		T5	27		T8	28
valid_sources[0x45]	415147	1			T4	2		T5	41		T8	14
valid_sources[0x46]	415132	1			T5	37		T6	6		T8	23
valid_sources[0x47]	411408	1			T4	1		T5	43		T6	7
valid_sources[0x48]	413426	1			T4	4		T5	35		T6	2
valid_sources[0x49]	415240	1			T4	3		T5	23		T8	27
valid_sources[0x4a]	415748	1			T5	36		T8	30		T10	69
valid_sources[0x4b]	413337	1			T4	2		T5	36		T6	10
valid_sources[0x4c]	414196	1			T5	20		T8	10		T10	72
valid_sources[0x4d]	414751	1			T5	34		T7	112		T8	28
valid_sources[0x4e]	415965	1			T4	1		T5	43		T6	14
valid_sources[0x4f]	415710	1			T4	1		T5	40		T8	27
valid_sources[0x50]	411083	1			T4	1		T5	33		T6	5
valid_sources[0x51]	414499	1			T4	1		T5	22		T6	13
valid_sources[0x52]	696811	1			T5	32		T6	3		T8	33
valid_sources[0x53]	411968	1			T4	2		T5	22		T6	1
valid_sources[0x54]	571036	1			T5	44		T8	20		T10	55
valid_sources[0x55]	417387	1			T4	2		T5	46		T6	24
valid_sources[0x56]	415865	1			T4	1		T5	50		T8	17
valid_sources[0x57]	415985	1			T4	5		T5	28		T6	1
valid_sources[0x58]	417077	1			T4	4		T5	39		T7	1
valid_sources[0x59]	416087	1			T5	35		T7	15		T8	17
valid_sources[0x5a]	437446	1			T4	2		T5	42		T6	3
valid_sources[0x5b]	719622	1			T5	32		T6	5		T7	17
valid_sources[0x5c]	436148	1			T5	38		T8	37		T10	60
valid_sources[0x5d]	417181	1			T4	4		T5	32		T8	25
valid_sources[0x5e]	649006	1			T4	6		T5	38		T6	5
valid_sources[0x5f]	505333	1			T5	22		T8	24		T10	57
valid_sources[0x60]	415183	1			T4	2		T5	45		T6	5
valid_sources[0x61]	411640	1			T4	4		T5	48		T6	4
valid_sources[0x62]	415711	1			T5	37		T6	22		T7	234
valid_sources[0x63]	849937	1			T4	2		T5	51		T6	2
valid_sources[0x64]	411074	1			T4	1		T5	46		T7	1
valid_sources[0x65]	417380	1			T5	43		T6	11		T8	50
valid_sources[0x66]	411341	1			T4	3		T5	50		T6	2
valid_sources[0x67]	415529	1			T4	1		T5	32		T7	28
valid_sources[0x68]	412859	1			T4	1		T5	32		T8	25
valid_sources[0x69]	413474	1			T4	5		T5	51		T6	3
valid_sources[0x6a]	413309	1			T4	2		T5	41		T6	1
valid_sources[0x6b]	796135	1			T3	1		T4	1		T5	32
valid_sources[0x6c]	2299370	1			T4	2		T5	44		T6	2
valid_sources[0x6d]	410649	1			T4	2		T5	45		T6	2
valid_sources[0x6e]	412082	1			T4	4		T5	25		T6	6
valid_sources[0x6f]	426522	1			T5	30		T6	2		T8	51
valid_sources[0x70]	413646	1			T4	3		T5	48		T6	3
valid_sources[0x71]	541187	1			T4	3		T5	40		T8	12
valid_sources[0x72]	417205	1			T5	24		T6	1		T8	25
valid_sources[0x73]	415588	1			T4	3		T5	33		T6	10
valid_sources[0x74]	461880	1			T5	27		T6	3		T7	48
valid_sources[0x75]	442793	1			T5	34		T8	29		T10	50
valid_sources[0x76]	4276634	1			T4	1		T5	29		T6	4
valid_sources[0x77]	412471	1			T4	2		T5	39		T6	4
valid_sources[0x78]	1603919	1			T5	32		T6	7		T7	152
valid_sources[0x79]	934144	1			T4	2		T5	35		T6	15
valid_sources[0x7a]	413945	1			T5	33		T6	3		T7	1
valid_sources[0x7b]	425311	1			T2	1		T4	1		T5	34
valid_sources[0x7c]	523995	1			T5	33		T7	370		T8	37
valid_sources[0x7d]	415299	1			T5	34		T8	14		T10	72
valid_sources[0x7e]	414701	1			T4	1		T5	34		T6	6
valid_sources[0x7f]	415669	1			T4	1		T5	32		T6	1
valid_sources[0x80]	413880	1			T4	2		T5	48		T6	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68473240

1

T2

1

T4

184

T5

2383

values[0x0]

all_enables

biggest_size

60365

1

T4

4

T5

3011

T6

1

values[0x1]

all_enables

biggest_size

58965

1

T4

1

T5

3121

T6

4