Unified Coverage Report :: Module :: timer_core

Module : timer_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/timer_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_harts[0].u_core	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.gen_harts[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : timer_core

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
ALWAYS	28	7	7	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	45	1	1	100.00

27                        always_ff @(posedge clk_i or negedge rst_ni) begin : generate_tick
28         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
29         1/1                tick_count <= 12'h0;
           Tests:       T1 T2 T3 
30         1/1              end else if (!active) begin
           Tests:       T1 T2 T3 
31         1/1                tick_count <= 12'h0;
           Tests:       T1 T2 T3 
32         1/1              end else if (tick_count == prescaler) begin
           Tests:       T5 T6 T7 
33         1/1                tick_count <= 12'h0;
           Tests:       T5 T6 T7 
34                          end else begin
35         1/1                tick_count <= tick_count + 1'b1;
           Tests:       T5 T6 T7 
36                          end
37                        end
38                      
39         1/1            assign tick = active & (tick_count >= prescaler);
           Tests:       T1 T2 T3 
40                      
41         1/1            assign mtime_d = mtime + 64'(step);
           Tests:       T1 T2 T3 
42                      
43                        // interrupt is generated if mtime is greater than or equal to mtimecmp
44                        for (genvar t = 0 ; t < N ; t++) begin : gen_intr
45         1/1              assign intr[t] = active & (mtime >= mtimecmp[t]);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : timer_core

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       32
 EXPRESSION (tick_count == prescaler)
            ------------1------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       39
 EXPRESSION (active & (tick_count >= prescaler))
             ---1--   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       45
 EXPRESSION (active & (mtime >= mtimecmp[0]))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T20,T11

---

Branch Coverage for Module : timer_core

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	4	4	100.00

28             if (!rst_ni) begin
               -1-  
29               tick_count <= 12'h0;
                 ==>
30             end else if (!active) begin
                        -2-  
31               tick_count <= 12'h0;
                 ==>
32             end else if (tick_count == prescaler) begin
                        -3-  
33               tick_count <= 12'h0;
                 ==>
34             end else begin
35               tick_count <= tick_count + 1'b1;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T6,T7