Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	160600	0	0
cfg0_rd_A	2147483647	2235	0	0
compare_lower0_0_rd_A	2147483647	1921	0	0
compare_upper0_0_rd_A	2147483647	1860	0	0
ctrl_rd_A	2147483647	1939	0	0
intr_enable0_rd_A	2147483647	2943	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	160600	0	0
T5	243132	10263	0	0
T6	794422	0	0	0
T7	190181	5987	0	0
T8	297465	0	0	0
T9	8592	0	0	0
T10	452322	19021	0	0
T11	423605	0	0	0
T14	4074	0	0	0
T20	303566	0	0	0
T21	208773	0	0	0
T23	0	2306	0	0
T24	0	12305	0	0
T25	0	5540	0	0
T26	0	11956	0	0
T27	0	20657	0	0
T28	0	1998	0	0
T29	0	5521	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2235	0	0
T18	0	7	0	0
T29	186888	43	0	0
T30	0	40	0	0
T31	0	7	0	0
T32	0	117	0	0
T33	0	18	0	0
T34	0	5	0	0
T35	0	21	0	0
T36	0	1	0	0
T37	0	9	0	0
T38	510140	0	0	0
T39	702120	0	0	0
T40	163911	0	0	0
T41	106680	0	0	0
T42	218920	0	0	0
T43	548160	0	0	0
T44	681343	0	0	0
T45	368235	0	0	0
T46	200027	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1921	0	0
T18	0	5	0	0
T29	186888	81	0	0
T30	0	36	0	0
T31	0	19	0	0
T32	0	151	0	0
T33	0	12	0	0
T35	0	9	0	0
T37	0	4	0	0
T38	510140	0	0	0
T39	702120	0	0	0
T40	163911	0	0	0
T41	106680	0	0	0
T42	218920	0	0	0
T43	548160	0	0	0
T44	681343	0	0	0
T45	368235	0	0	0
T46	200027	0	0	0
T47	0	8	0	0
T48	0	9	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1860	0	0
T18	0	3	0	0
T29	186888	91	0	0
T30	0	38	0	0
T31	0	15	0	0
T32	0	95	0	0
T33	0	35	0	0
T34	0	8	0	0
T35	0	12	0	0
T38	510140	0	0	0
T39	702120	0	0	0
T40	163911	0	0	0
T41	106680	0	0	0
T42	218920	0	0	0
T43	548160	0	0	0
T44	681343	0	0	0
T45	368235	0	0	0
T46	200027	0	0	0
T47	0	4	0	0
T48	0	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1939	0	0
T18	0	3	0	0
T29	186888	72	0	0
T30	0	27	0	0
T31	0	34	0	0
T32	0	165	0	0
T33	0	9	0	0
T34	0	5	0	0
T35	0	10	0	0
T38	510140	0	0	0
T39	702120	0	0	0
T40	163911	0	0	0
T41	106680	0	0	0
T42	218920	0	0	0
T43	548160	0	0	0
T44	681343	0	0	0
T45	368235	0	0	0
T46	200027	0	0	0
T47	0	12	0	0
T49	0	2	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2943	0	0
T24	272846	0	0	0
T25	133084	0	0	0
T26	381884	0	0	0
T29	0	148	0	0
T41	0	7	0	0
T45	0	57	0	0
T50	1597	17	0	0
T51	0	87	0	0
T52	0	30	0	0
T53	0	10	0	0
T54	0	77	0	0
T55	0	18	0	0
T56	0	66	0	0
T57	176018	0	0	0
T58	274529	0	0	0
T59	468305	0	0	0
T60	163904	0	0	0
T61	467072	0	0	0
T62	324225	0	0	0