Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66437442	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

66589057

1

T1

1

T2

49

T4

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	132888468	1			T1	1		T2	85		T3	1
values[0x0]	66631	1			T2	7		T4	12		T8	8
values[0x1]	71400	1			T2	12		T4	9		T8	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53091005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

79935494

1

T1

1

T2

58

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	405566	1			T8	10		T9	5		T10	26
valid_sources[0x01]	377840	1			T8	7		T9	3		T10	18
valid_sources[0x02]	376679	1			T8	7		T9	6		T10	9
valid_sources[0x03]	381060	1			T8	13		T9	6		T10	5
valid_sources[0x04]	382038	1			T2	3		T8	8		T9	1
valid_sources[0x05]	389639	1			T8	7		T9	12		T10	37
valid_sources[0x06]	380843	1			T8	6		T9	5		T10	4
valid_sources[0x07]	441197	1			T8	3		T9	5		T10	8
valid_sources[0x08]	420515	1			T8	6		T9	38		T10	4
valid_sources[0x09]	379768	1			T2	1		T7	1		T8	10
valid_sources[0x0a]	376003	1			T4	26		T8	5		T9	14
valid_sources[0x0b]	375697	1			T8	4		T9	2		T10	6
valid_sources[0x0c]	493748	1			T8	8		T9	1		T14	20
valid_sources[0x0d]	378599	1			T8	6		T9	16		T10	27
valid_sources[0x0e]	1415034	1			T2	1		T8	4		T9	10
valid_sources[0x0f]	375384	1			T1	1		T8	4		T9	4
valid_sources[0x10]	380084	1			T8	4		T9	2		T10	14
valid_sources[0x11]	403382	1			T8	7		T9	9		T10	3
valid_sources[0x12]	392056	1			T8	14		T9	3		T10	27
valid_sources[0x13]	379871	1			T8	9		T9	3		T10	4
valid_sources[0x14]	377391	1			T8	6		T9	1		T10	30
valid_sources[0x15]	380192	1			T8	8		T9	9		T14	22
valid_sources[0x16]	377610	1			T8	8		T9	10		T10	1
valid_sources[0x17]	378489	1			T8	13		T9	19		T10	14
valid_sources[0x18]	377882	1			T8	4		T9	3		T10	14
valid_sources[0x19]	377366	1			T8	4		T9	14		T10	4
valid_sources[0x1a]	399036	1			T8	12		T9	6		T10	31
valid_sources[0x1b]	379517	1			T8	9		T9	7		T10	27
valid_sources[0x1c]	377779	1			T8	8		T9	4		T10	21
valid_sources[0x1d]	379864	1			T8	10		T9	18		T10	1
valid_sources[0x1e]	377097	1			T8	5		T9	18		T10	19
valid_sources[0x1f]	376030	1			T8	8		T9	8		T10	17
valid_sources[0x20]	382965	1			T8	6		T9	5		T10	7
valid_sources[0x21]	380105	1			T8	2		T9	5		T10	8
valid_sources[0x22]	1166810	1			T2	2		T8	7		T9	6
valid_sources[0x23]	381757	1			T8	10		T9	10		T10	53
valid_sources[0x24]	380439	1			T2	2		T8	10		T10	11
valid_sources[0x25]	2378887	1			T8	8		T9	11		T10	1
valid_sources[0x26]	377861	1			T8	9		T9	11		T10	6
valid_sources[0x27]	586003	1			T8	5		T9	6		T10	46
valid_sources[0x28]	381887	1			T8	7		T9	7		T10	6
valid_sources[0x29]	381880	1			T8	4		T9	18		T10	27
valid_sources[0x2a]	379344	1			T8	13		T9	16		T10	13
valid_sources[0x2b]	375416	1			T8	5		T9	8		T10	9
valid_sources[0x2c]	1144115	1			T8	10		T9	1		T10	9
valid_sources[0x2d]	1574948	1			T8	10		T9	2		T10	19
valid_sources[0x2e]	382149	1			T8	6		T9	7		T10	16
valid_sources[0x2f]	382005	1			T2	6		T8	8		T9	3
valid_sources[0x30]	809598	1			T8	4		T9	9		T10	4
valid_sources[0x31]	396304	1			T8	3		T9	17		T10	16
valid_sources[0x32]	378564	1			T2	7		T8	4		T9	5
valid_sources[0x33]	429357	1			T2	1		T8	6		T9	2
valid_sources[0x34]	380302	1			T8	11		T9	15		T10	6
valid_sources[0x35]	381108	1			T8	9		T9	1		T10	22
valid_sources[0x36]	378882	1			T8	12		T9	11		T10	14
valid_sources[0x37]	378711	1			T8	2		T9	3		T10	22
valid_sources[0x38]	1329425	1			T8	7		T9	5		T10	19
valid_sources[0x39]	378234	1			T8	2		T9	3		T10	9
valid_sources[0x3a]	381646	1			T8	10		T9	4		T10	10
valid_sources[0x3b]	382496	1			T8	10		T9	3		T10	13
valid_sources[0x3c]	379289	1			T2	1		T8	4		T9	10
valid_sources[0x3d]	380105	1			T8	4		T9	2		T10	25
valid_sources[0x3e]	376518	1			T8	8		T9	2		T14	11
valid_sources[0x3f]	377063	1			T8	11		T9	13		T10	7
valid_sources[0x40]	400032	1			T8	7		T9	3		T10	18
valid_sources[0x41]	380402	1			T2	4		T8	9		T10	53
valid_sources[0x42]	381565	1			T8	7		T9	4		T10	35
valid_sources[0x43]	2558253	1			T8	2		T9	2		T10	16
valid_sources[0x44]	1692694	1			T2	1		T8	10		T9	7
valid_sources[0x45]	860896	1			T8	9		T9	12		T10	7
valid_sources[0x46]	379474	1			T8	12		T10	8		T14	20
valid_sources[0x47]	378812	1			T2	2		T8	8		T9	15
valid_sources[0x48]	478996	1			T8	7		T9	3		T10	18
valid_sources[0x49]	3039621	1			T8	8		T9	10		T10	23
valid_sources[0x4a]	388421	1			T8	9		T9	9		T10	1
valid_sources[0x4b]	380833	1			T8	14		T9	22		T10	19
valid_sources[0x4c]	378948	1			T8	13		T9	6		T14	32
valid_sources[0x4d]	379575	1			T8	5		T9	10		T10	15
valid_sources[0x4e]	398537	1			T8	10		T9	10		T10	19
valid_sources[0x4f]	455247	1			T2	2		T8	11		T9	1
valid_sources[0x50]	382364	1			T8	11		T9	5		T10	2
valid_sources[0x51]	378227	1			T8	4		T9	8		T10	14
valid_sources[0x52]	382469	1			T8	7		T9	19		T10	18
valid_sources[0x53]	379341	1			T8	3		T9	5		T10	18
valid_sources[0x54]	379729	1			T8	7		T9	2		T14	10
valid_sources[0x55]	378898	1			T8	5		T9	13		T10	4
valid_sources[0x56]	376521	1			T8	6		T9	7		T10	6
valid_sources[0x57]	377382	1			T2	1		T8	7		T9	7
valid_sources[0x58]	378421	1			T8	2		T9	3		T10	8
valid_sources[0x59]	377833	1			T2	2		T8	7		T9	14
valid_sources[0x5a]	380230	1			T8	6		T9	21		T10	5
valid_sources[0x5b]	692126	1			T8	8		T9	12		T10	5
valid_sources[0x5c]	379302	1			T8	12		T9	11		T10	18
valid_sources[0x5d]	381377	1			T8	5		T9	10		T10	21
valid_sources[0x5e]	380069	1			T2	2		T8	7		T9	13
valid_sources[0x5f]	380782	1			T2	2		T8	5		T9	11
valid_sources[0x60]	379317	1			T8	7		T9	16		T10	22
valid_sources[0x61]	390907	1			T8	14		T9	32		T10	8
valid_sources[0x62]	378180	1			T2	4		T8	5		T9	13
valid_sources[0x63]	563634	1			T8	7		T9	3		T10	20
valid_sources[0x64]	379319	1			T8	13		T10	1		T14	15
valid_sources[0x65]	379539	1			T8	3		T9	2		T10	12
valid_sources[0x66]	379431	1			T8	9		T9	14		T14	10
valid_sources[0x67]	379465	1			T8	5		T9	13		T10	20
valid_sources[0x68]	1054540	1			T8	5		T9	6		T10	48
valid_sources[0x69]	411397	1			T8	10		T9	2		T10	3
valid_sources[0x6a]	378525	1			T2	3		T8	2		T9	6
valid_sources[0x6b]	379468	1			T8	14		T9	7		T10	29
valid_sources[0x6c]	417643	1			T8	6		T9	5		T10	14
valid_sources[0x6d]	375933	1			T8	1		T9	12		T10	11
valid_sources[0x6e]	386583	1			T8	5		T9	7		T10	35
valid_sources[0x6f]	378967	1			T8	5		T9	1		T10	9
valid_sources[0x70]	378714	1			T8	9		T9	5		T10	9
valid_sources[0x71]	382895	1			T8	13		T9	7		T10	3
valid_sources[0x72]	4278834	1			T8	4		T9	7		T10	6
valid_sources[0x73]	373661	1			T8	6		T9	4		T10	3
valid_sources[0x74]	377869	1			T8	11		T9	14		T10	38
valid_sources[0x75]	380395	1			T8	3		T9	2		T10	6
valid_sources[0x76]	377075	1			T8	11		T9	1		T10	20
valid_sources[0x77]	379316	1			T8	10		T9	13		T10	11
valid_sources[0x78]	379308	1			T8	8		T9	13		T10	19
valid_sources[0x79]	764852	1			T8	6		T9	4		T10	23
valid_sources[0x7a]	378918	1			T8	13		T9	11		T10	12
valid_sources[0x7b]	784304	1			T8	8		T9	8		T10	2
valid_sources[0x7c]	374669	1			T8	6		T9	6		T14	22
valid_sources[0x7d]	379411	1			T8	3		T9	16		T14	3
valid_sources[0x7e]	380159	1			T8	11		T9	4		T10	10
valid_sources[0x7f]	1923077	1			T2	7		T8	10		T10	11
valid_sources[0x80]	377087	1			T8	4		T9	8		T10	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66468797

1

T1

1

T2

35

T4

3

values[0x0]

all_enables

biggest_size

61126

1

T2

4

T4

11

T8

6

values[0x1]

all_enables

biggest_size

59134

1

T2

10

T4

5

T8

5