Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	159298	0	0
cfg0_rd_A	2147483647	1841	0	0
compare_lower0_0_rd_A	2147483647	1682	0	0
compare_upper0_0_rd_A	2147483647	1722	0	0
ctrl_rd_A	2147483647	1588	0	0
intr_enable0_rd_A	2147483647	2561	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	159298	0	0
T11	480397	21455	0	0
T13	0	6508	0	0
T16	578511	0	0	0
T17	0	20638	0	0
T23	197220	0	0	0
T24	0	12298	0	0
T25	0	2114	0	0
T26	0	18568	0	0
T27	0	12506	0	0
T28	0	2022	0	0
T29	0	9403	0	0
T30	0	10643	0	0
T31	246576	0	0	0
T32	323980	0	0	0
T33	272202	0	0	0
T34	253080	0	0	0
T35	486255	0	0	0
T36	10673	0	0	0
T37	384024	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1841	0	0
T19	0	146	0	0
T27	413750	120	0	0
T28	0	39	0	0
T30	0	113	0	0
T38	0	141	0	0
T39	0	80	0	0
T40	0	9	0	0
T41	0	4	0	0
T42	0	20	0	0
T43	0	19	0	0
T44	209252	0	0	0
T45	132008	0	0	0
T46	122972	0	0	0
T47	388876	0	0	0
T48	203041	0	0	0
T49	133422	0	0	0
T50	433938	0	0	0
T51	100220	0	0	0
T52	116337	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1682	0	0
T19	0	116	0	0
T27	413750	76	0	0
T28	0	45	0	0
T30	0	131	0	0
T38	0	89	0	0
T39	0	93	0	0
T40	0	11	0	0
T41	0	12	0	0
T42	0	17	0	0
T43	0	51	0	0
T44	209252	0	0	0
T45	132008	0	0	0
T46	122972	0	0	0
T47	388876	0	0	0
T48	203041	0	0	0
T49	133422	0	0	0
T50	433938	0	0	0
T51	100220	0	0	0
T52	116337	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1722	0	0
T19	0	132	0	0
T27	413750	95	0	0
T28	0	56	0	0
T30	0	148	0	0
T38	0	108	0	0
T39	0	71	0	0
T41	0	4	0	0
T42	0	7	0	0
T43	0	18	0	0
T44	209252	0	0	0
T45	132008	0	0	0
T46	122972	0	0	0
T47	388876	0	0	0
T48	203041	0	0	0
T49	133422	0	0	0
T50	433938	0	0	0
T51	100220	0	0	0
T52	116337	0	0	0
T53	0	24	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1588	0	0
T19	0	113	0	0
T27	413750	85	0	0
T28	0	33	0	0
T30	0	104	0	0
T38	0	93	0	0
T39	0	103	0	0
T40	0	1	0	0
T41	0	12	0	0
T42	0	22	0	0
T43	0	50	0	0
T44	209252	0	0	0
T45	132008	0	0	0
T46	122972	0	0	0
T47	388876	0	0	0
T48	203041	0	0	0
T49	133422	0	0	0
T50	433938	0	0	0
T51	100220	0	0	0
T52	116337	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2561	0	0
T27	0	274	0	0
T28	0	143	0	0
T30	0	288	0	0
T38	0	121	0	0
T54	999634	48	0	0
T55	0	42	0	0
T56	0	41	0	0
T57	0	6	0	0
T58	0	17	0	0
T59	0	3	0	0
T60	335545	0	0	0
T61	645293	0	0	0
T62	623365	0	0	0
T63	2264	0	0	0
T64	118111	0	0	0
T65	289430	0	0	0
T66	5891	0	0	0
T67	703701	0	0	0
T68	826924	0	0	0