Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	68283040	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

68403669

1

T1

11

T3

91

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136571070	1			T1	9		T2	1		T3	181
values[0x0]	55959	1			T1	5		T3	2		T8	27
values[0x1]	59680	1			T1	5		T3	4		T8	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54558983	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

82127726

1

T1

11

T3

108

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	405836	1			T3	2		T13	2		T12	16
valid_sources[0x01]	528620	1			T3	2		T12	21		T33	34
valid_sources[0x02]	404069	1			T3	5		T13	1		T12	30
valid_sources[0x03]	692406	1			T3	1		T13	1		T12	18
valid_sources[0x04]	403717	1			T3	1		T13	1		T12	20
valid_sources[0x05]	406426	1			T3	1		T12	25		T33	41
valid_sources[0x06]	407200	1			T12	21		T33	36		T34	44
valid_sources[0x07]	448851	1			T12	25		T33	22		T34	43
valid_sources[0x08]	427104	1			T3	1		T13	1		T12	14
valid_sources[0x09]	403766	1			T3	1		T13	2		T12	22
valid_sources[0x0a]	425362	1			T13	1		T12	32		T33	11
valid_sources[0x0b]	402549	1			T12	18		T33	22		T34	33
valid_sources[0x0c]	859574	1			T5	1		T12	23		T33	20
valid_sources[0x0d]	1195438	1			T3	1		T12	26		T33	11
valid_sources[0x0e]	406969	1			T3	2		T13	1		T12	24
valid_sources[0x0f]	402365	1			T3	2		T13	1		T12	22
valid_sources[0x10]	403650	1			T3	2		T13	4		T12	26
valid_sources[0x11]	406024	1			T9	1		T13	2		T12	23
valid_sources[0x12]	543799	1			T9	1		T13	2		T12	19
valid_sources[0x13]	408077	1			T3	5		T12	21		T33	22
valid_sources[0x14]	403927	1			T3	1		T13	1		T12	21
valid_sources[0x15]	407349	1			T12	19		T33	25		T34	30
valid_sources[0x16]	682695	1			T3	1		T12	26		T33	48
valid_sources[0x17]	1596525	1			T3	1		T12	27		T33	18
valid_sources[0x18]	404918	1			T3	6		T13	1		T12	15
valid_sources[0x19]	406949	1			T3	1		T12	25		T33	22
valid_sources[0x1a]	404208	1			T3	1		T12	27		T33	26
valid_sources[0x1b]	401699	1			T3	1		T12	18		T33	21
valid_sources[0x1c]	404088	1			T3	2		T9	1		T13	1
valid_sources[0x1d]	403422	1			T12	23		T33	20		T34	41
valid_sources[0x1e]	404641	1			T12	34		T33	22		T34	38
valid_sources[0x1f]	402428	1			T12	27		T33	51		T34	26
valid_sources[0x20]	403386	1			T13	1		T12	15		T33	49
valid_sources[0x21]	405214	1			T13	1		T12	16		T33	23
valid_sources[0x22]	404062	1			T13	1		T12	19		T33	33
valid_sources[0x23]	405350	1			T3	1		T13	1		T12	20
valid_sources[0x24]	408712	1			T13	1		T12	22		T33	33
valid_sources[0x25]	408192	1			T3	1		T12	24		T33	20
valid_sources[0x26]	403953	1			T3	1		T12	21		T33	37
valid_sources[0x27]	1290489	1			T3	1		T13	2		T12	15
valid_sources[0x28]	406016	1			T3	2		T12	22		T33	39
valid_sources[0x29]	1019239	1			T3	1		T9	1		T13	2
valid_sources[0x2a]	404095	1			T3	1		T9	1		T13	1
valid_sources[0x2b]	406950	1			T3	2		T12	24		T33	14
valid_sources[0x2c]	406164	1			T13	1		T12	17		T33	27
valid_sources[0x2d]	404339	1			T12	22		T33	27		T34	48
valid_sources[0x2e]	404301	1			T3	2		T12	21		T33	30
valid_sources[0x2f]	405971	1			T13	1		T12	23		T33	36
valid_sources[0x30]	708676	1			T3	2		T13	1		T12	27
valid_sources[0x31]	756537	1			T3	1		T13	1		T12	19
valid_sources[0x32]	2581178	1			T3	3		T13	4		T12	28
valid_sources[0x33]	406513	1			T12	24		T33	47		T34	28
valid_sources[0x34]	406913	1			T12	22		T33	39		T34	40
valid_sources[0x35]	405612	1			T9	1		T13	1		T12	24
valid_sources[0x36]	403720	1			T12	25		T33	42		T34	44
valid_sources[0x37]	405672	1			T13	1		T12	18		T23	3014
valid_sources[0x38]	403686	1			T12	32		T33	25		T34	41
valid_sources[0x39]	575729	1			T3	1		T13	1		T12	24
valid_sources[0x3a]	420152	1			T3	2		T12	20		T33	30
valid_sources[0x3b]	404229	1			T3	1		T12	27		T33	33
valid_sources[0x3c]	404562	1			T13	1		T12	26		T33	27
valid_sources[0x3d]	405018	1			T3	1		T12	21		T33	19
valid_sources[0x3e]	632580	1			T9	1		T12	23		T33	26
valid_sources[0x3f]	406862	1			T13	1		T12	31		T33	18
valid_sources[0x40]	415106	1			T3	1		T9	1		T12	22
valid_sources[0x41]	403453	1			T13	1		T12	12		T33	30
valid_sources[0x42]	402883	1			T3	1		T13	1		T12	28
valid_sources[0x43]	402986	1			T3	2		T9	1		T13	1
valid_sources[0x44]	404262	1			T3	1		T9	2		T12	14
valid_sources[0x45]	403958	1			T3	2		T12	15		T33	48
valid_sources[0x46]	404363	1			T3	1		T13	2		T12	26
valid_sources[0x47]	406136	1			T3	3		T13	1		T12	15
valid_sources[0x48]	406150	1			T12	26		T33	42		T34	40
valid_sources[0x49]	403205	1			T3	2		T12	23		T33	29
valid_sources[0x4a]	630134	1			T3	3		T12	20		T33	24
valid_sources[0x4b]	458480	1			T13	1		T12	25		T33	21
valid_sources[0x4c]	403313	1			T3	3		T13	2		T12	19
valid_sources[0x4d]	403280	1			T12	18		T33	43		T34	23
valid_sources[0x4e]	406655	1			T12	27		T33	28		T34	32
valid_sources[0x4f]	403193	1			T12	28		T33	45		T34	32
valid_sources[0x50]	403516	1			T3	1		T12	24		T33	18
valid_sources[0x51]	1073446	1			T9	1		T13	1		T12	19
valid_sources[0x52]	407974	1			T13	2		T12	30		T33	28
valid_sources[0x53]	404426	1			T3	1		T12	26		T33	33
valid_sources[0x54]	403909	1			T3	1		T13	1		T12	27
valid_sources[0x55]	408315	1			T12	18		T33	26		T34	27
valid_sources[0x56]	471419	1			T3	1		T13	1		T12	16
valid_sources[0x57]	408845	1			T3	1		T13	1		T12	16
valid_sources[0x58]	401595	1			T9	1		T12	20		T33	26
valid_sources[0x59]	3267318	1			T3	2		T13	1		T12	28
valid_sources[0x5a]	404134	1			T10	38		T13	2		T12	25
valid_sources[0x5b]	403303	1			T3	1		T13	2		T12	24
valid_sources[0x5c]	731527	1			T3	1		T12	36		T33	35
valid_sources[0x5d]	524700	1			T3	1		T9	1		T13	1
valid_sources[0x5e]	406879	1			T13	1		T12	18		T33	26
valid_sources[0x5f]	1091981	1			T9	1		T12	27		T33	23
valid_sources[0x60]	416461	1			T13	1		T12	23		T33	40
valid_sources[0x61]	405670	1			T3	2		T12	17		T33	32
valid_sources[0x62]	979962	1			T3	1		T13	1		T12	16
valid_sources[0x63]	402974	1			T12	27		T33	36		T34	34
valid_sources[0x64]	404435	1			T9	1		T12	28		T33	33
valid_sources[0x65]	402170	1			T9	1		T12	18		T33	17
valid_sources[0x66]	2469516	1			T3	1		T12	31		T33	41
valid_sources[0x67]	402885	1			T3	2		T12	21		T33	27
valid_sources[0x68]	403816	1			T12	21		T33	27		T34	28
valid_sources[0x69]	473132	1			T3	1		T12	26		T33	44
valid_sources[0x6a]	406213	1			T13	1		T12	20		T33	23
valid_sources[0x6b]	612528	1			T3	1		T13	1		T12	31
valid_sources[0x6c]	923955	1			T3	2		T12	15		T33	38
valid_sources[0x6d]	572543	1			T3	1		T12	26		T33	35
valid_sources[0x6e]	403792	1			T12	20		T33	21		T34	35
valid_sources[0x6f]	417906	1			T3	1		T12	16		T33	29
valid_sources[0x70]	406158	1			T13	1		T12	22		T33	30
valid_sources[0x71]	404354	1			T9	1		T13	1		T12	13
valid_sources[0x72]	574095	1			T12	27		T33	26		T34	42
valid_sources[0x73]	404986	1			T12	29		T33	28		T34	36
valid_sources[0x74]	403838	1			T12	30		T33	28		T34	22
valid_sources[0x75]	406420	1			T3	1		T13	1		T12	17
valid_sources[0x76]	403206	1			T13	2		T12	20		T33	32
valid_sources[0x77]	402170	1			T3	4		T12	17		T33	22
valid_sources[0x78]	403098	1			T3	1		T8	267		T13	1
valid_sources[0x79]	406327	1			T9	1		T13	1		T12	27
valid_sources[0x7a]	406718	1			T12	28		T33	36		T34	34
valid_sources[0x7b]	404721	1			T12	24		T33	42		T34	29
valid_sources[0x7c]	695533	1			T3	2		T12	13		T33	26
valid_sources[0x7d]	404658	1			T12	20		T33	24		T34	20
valid_sources[0x7e]	405137	1			T3	1		T9	1		T12	35
valid_sources[0x7f]	407905	1			T12	22		T33	26		T34	37
valid_sources[0x80]	710613	1			T3	3		T12	20		T33	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68303884

1

T1

6

T3

85

T4

1

values[0x0]

all_enables

biggest_size

50722

1

T1

2

T3

2

T8

17

values[0x1]

all_enables

biggest_size

49063

1

T1

3

T3

4

T8

19