Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	124172	0	0
cfg0_rd_A	2147483647	2150	0	0
compare_lower0_0_rd_A	2147483647	1717	0	0
compare_upper0_0_rd_A	2147483647	1706	0	0
ctrl_rd_A	2147483647	1702	0	0
intr_enable0_rd_A	2147483647	2967	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	124172	0	0
T12	129745	6203	0	0
T14	211718	0	0	0
T15	466991	0	0	0
T17	151800	0	0	0
T18	251280	11191	0	0
T19	0	4405	0	0
T23	286445	0	0	0
T26	0	12442	0	0
T27	0	10993	0	0
T28	0	6717	0	0
T29	0	24683	0	0
T30	0	5813	0	0
T31	0	1524	0	0
T32	0	5145	0	0
T33	381364	0	0	0
T34	347361	0	0	0
T35	439351	0	0	0
T36	295285	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2150	0	0
T19	157801	74	0	0
T20	0	87	0	0
T25	0	1	0	0
T37	0	118	0	0
T38	0	40	0	0
T39	0	446	0	0
T40	0	3	0	0
T41	0	167	0	0
T42	0	33	0	0
T43	0	3	0	0
T44	128538	0	0	0
T45	136719	0	0	0
T46	19854	0	0	0
T47	112300	0	0	0
T48	109335	0	0	0
T49	617177	0	0	0
T50	111762	0	0	0
T51	385774	0	0	0
T52	134926	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1717	0	0
T19	157801	83	0	0
T20	0	65	0	0
T37	0	175	0	0
T38	0	23	0	0
T39	0	413	0	0
T40	0	8	0	0
T41	0	144	0	0
T42	0	38	0	0
T44	128538	0	0	0
T45	136719	0	0	0
T46	19854	0	0	0
T47	112300	0	0	0
T48	109335	0	0	0
T49	617177	0	0	0
T50	111762	0	0	0
T51	385774	0	0	0
T52	134926	0	0	0
T53	0	1	0	0
T54	0	9	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1706	0	0
T19	157801	51	0	0
T20	0	51	0	0
T37	0	110	0	0
T38	0	15	0	0
T39	0	443	0	0
T40	0	6	0	0
T41	0	150	0	0
T42	0	20	0	0
T43	0	5	0	0
T44	128538	0	0	0
T45	136719	0	0	0
T46	19854	0	0	0
T47	112300	0	0	0
T48	109335	0	0	0
T49	617177	0	0	0
T50	111762	0	0	0
T51	385774	0	0	0
T52	134926	0	0	0
T54	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1702	0	0
T19	157801	39	0	0
T20	0	71	0	0
T37	0	108	0	0
T38	0	10	0	0
T39	0	474	0	0
T40	0	6	0	0
T41	0	128	0	0
T42	0	31	0	0
T44	128538	0	0	0
T45	136719	0	0	0
T46	19854	0	0	0
T47	112300	0	0	0
T48	109335	0	0	0
T49	617177	0	0	0
T50	111762	0	0	0
T51	385774	0	0	0
T52	134926	0	0	0
T53	0	4	0	0
T54	0	7	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2967	0	0
T9	1902	25	0	0
T10	6477	0	0	0
T11	2175	0	0	0
T12	129745	0	0	0
T13	818113	0	0	0
T14	211718	0	0	0
T17	151800	0	0	0
T19	0	130	0	0
T23	286445	0	0	0
T33	381364	0	0	0
T34	347361	0	0	0
T37	0	242	0	0
T55	0	67	0	0
T56	0	13	0	0
T57	0	64	0	0
T58	0	42	0	0
T59	0	51	0	0
T60	0	26	0	0
T61	0	6	0	0