Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	72614646	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

72744708

1

T1

44223

T3

731

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	145218029	1			T1	88810		T2	1		T3	1447
values[0x0]	68138	1			T1	29		T3	7		T8	4
values[0x1]	73187	1			T1	23		T3	10		T8	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58027786	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

87331568

1

T1

53213

T2

1

T3

883

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	722950	1			T1	300		T3	4		T9	41
valid_sources[0x01]	661346	1			T1	330		T9	74		T10	33
valid_sources[0x02]	412373	1			T1	370		T3	8		T9	56
valid_sources[0x03]	419161	1			T1	315		T3	8		T9	46
valid_sources[0x04]	423472	1			T1	394		T3	7		T9	61
valid_sources[0x05]	416839	1			T1	306		T3	5		T9	56
valid_sources[0x06]	416627	1			T1	377		T3	12		T9	62
valid_sources[0x07]	1111196	1			T1	333		T3	7		T9	59
valid_sources[0x08]	415249	1			T1	351		T3	6		T9	50
valid_sources[0x09]	416785	1			T1	343		T3	5		T9	62
valid_sources[0x0a]	415692	1			T1	342		T3	7		T9	39
valid_sources[0x0b]	417656	1			T1	373		T3	2		T9	56
valid_sources[0x0c]	415897	1			T1	343		T3	5		T9	63
valid_sources[0x0d]	411953	1			T1	361		T3	7		T9	54
valid_sources[0x0e]	417365	1			T1	328		T3	4		T9	66
valid_sources[0x0f]	413928	1			T1	350		T3	5		T9	60
valid_sources[0x10]	474570	1			T1	372		T3	3		T9	54
valid_sources[0x11]	415118	1			T1	325		T3	3		T9	53
valid_sources[0x12]	419778	1			T1	334		T3	7		T9	52
valid_sources[0x13]	415484	1			T1	318		T2	1		T3	6
valid_sources[0x14]	415084	1			T1	338		T3	7		T9	47
valid_sources[0x15]	417696	1			T1	351		T3	5		T9	61
valid_sources[0x16]	417180	1			T1	320		T3	12		T9	65
valid_sources[0x17]	462691	1			T1	327		T3	9		T9	60
valid_sources[0x18]	431576	1			T1	332		T3	8		T9	74
valid_sources[0x19]	1122736	1			T1	310		T3	7		T9	70
valid_sources[0x1a]	671714	1			T1	325		T3	6		T9	60
valid_sources[0x1b]	629127	1			T1	348		T3	6		T9	59
valid_sources[0x1c]	416969	1			T1	307		T3	6		T9	53
valid_sources[0x1d]	413366	1			T1	368		T3	5		T9	56
valid_sources[0x1e]	415048	1			T1	345		T3	4		T9	43
valid_sources[0x1f]	417005	1			T1	330		T3	5		T9	75
valid_sources[0x20]	412175	1			T1	358		T3	4		T9	62
valid_sources[0x21]	414854	1			T1	345		T3	5		T9	56
valid_sources[0x22]	417985	1			T1	347		T3	3		T9	42
valid_sources[0x23]	438035	1			T1	356		T3	4		T9	48
valid_sources[0x24]	571577	1			T1	342		T3	6		T9	52
valid_sources[0x25]	416177	1			T1	338		T3	6		T9	60
valid_sources[0x26]	413224	1			T1	333		T3	4		T9	60
valid_sources[0x27]	413706	1			T1	342		T3	1		T9	68
valid_sources[0x28]	414782	1			T1	332		T3	3		T9	66
valid_sources[0x29]	1987487	1			T1	347		T3	7		T9	68
valid_sources[0x2a]	415024	1			T1	339		T3	6		T9	53
valid_sources[0x2b]	414000	1			T1	369		T3	5		T9	40
valid_sources[0x2c]	2964429	1			T1	321		T3	8		T9	50
valid_sources[0x2d]	468614	1			T1	328		T3	9		T9	46
valid_sources[0x2e]	415260	1			T1	337		T3	6		T9	66
valid_sources[0x2f]	415502	1			T1	358		T3	10		T9	49
valid_sources[0x30]	414616	1			T1	360		T3	8		T9	66
valid_sources[0x31]	433066	1			T1	339		T3	8		T9	69
valid_sources[0x32]	1612984	1			T1	374		T3	8		T9	53
valid_sources[0x33]	415722	1			T1	347		T3	5		T9	54
valid_sources[0x34]	416235	1			T1	352		T3	8		T9	58
valid_sources[0x35]	414927	1			T1	369		T3	3		T9	60
valid_sources[0x36]	476641	1			T1	383		T3	7		T9	52
valid_sources[0x37]	412506	1			T1	322		T3	4		T9	72
valid_sources[0x38]	430981	1			T1	312		T3	10		T9	69
valid_sources[0x39]	417000	1			T1	340		T3	3		T9	48
valid_sources[0x3a]	496690	1			T1	342		T3	3		T9	52
valid_sources[0x3b]	417743	1			T1	364		T3	6		T9	54
valid_sources[0x3c]	417057	1			T1	358		T3	3		T9	63
valid_sources[0x3d]	1089587	1			T1	348		T3	3		T9	53
valid_sources[0x3e]	416838	1			T1	343		T3	12		T9	49
valid_sources[0x3f]	417342	1			T1	356		T3	3		T9	48
valid_sources[0x40]	413711	1			T1	333		T3	6		T9	59
valid_sources[0x41]	416832	1			T1	335		T3	6		T9	71
valid_sources[0x42]	413397	1			T1	314		T3	7		T9	47
valid_sources[0x43]	415599	1			T1	329		T3	4		T9	60
valid_sources[0x44]	415319	1			T1	348		T3	5		T9	51
valid_sources[0x45]	450145	1			T1	357		T3	6		T9	47
valid_sources[0x46]	1114062	1			T1	375		T3	7		T9	62
valid_sources[0x47]	412680	1			T1	387		T3	3		T9	36
valid_sources[0x48]	416387	1			T1	356		T3	6		T9	48
valid_sources[0x49]	414407	1			T1	340		T3	3		T9	67
valid_sources[0x4a]	415202	1			T1	343		T3	7		T9	60
valid_sources[0x4b]	828112	1			T1	325		T3	7		T9	54
valid_sources[0x4c]	412535	1			T1	358		T3	5		T9	44
valid_sources[0x4d]	427735	1			T1	322		T3	3		T9	63
valid_sources[0x4e]	412340	1			T1	355		T3	5		T9	71
valid_sources[0x4f]	415607	1			T1	332		T3	5		T9	72
valid_sources[0x50]	1058518	1			T1	348		T3	7		T9	58
valid_sources[0x51]	414621	1			T1	357		T3	3		T9	60
valid_sources[0x52]	415932	1			T1	372		T3	6		T9	45
valid_sources[0x53]	415045	1			T1	362		T3	6		T9	56
valid_sources[0x54]	413251	1			T1	330		T3	4		T9	56
valid_sources[0x55]	414227	1			T1	342		T3	3		T9	63
valid_sources[0x56]	2834628	1			T1	388		T3	5		T9	53
valid_sources[0x57]	526636	1			T1	356		T3	1		T9	63
valid_sources[0x58]	416184	1			T1	319		T3	4		T9	43
valid_sources[0x59]	410571	1			T1	329		T3	6		T9	59
valid_sources[0x5a]	747784	1			T1	342		T3	5		T9	55
valid_sources[0x5b]	1018686	1			T1	340		T3	8		T9	46
valid_sources[0x5c]	429648	1			T1	357		T3	7		T9	70
valid_sources[0x5d]	412963	1			T1	336		T3	7		T9	53
valid_sources[0x5e]	429299	1			T1	356		T3	3		T9	53
valid_sources[0x5f]	452372	1			T1	330		T3	3		T9	47
valid_sources[0x60]	413924	1			T1	365		T3	4		T9	54
valid_sources[0x61]	418648	1			T1	317		T3	8		T9	44
valid_sources[0x62]	2567271	1			T1	330		T3	6		T9	57
valid_sources[0x63]	415815	1			T1	341		T3	6		T9	55
valid_sources[0x64]	413244	1			T1	359		T3	10		T9	52
valid_sources[0x65]	478695	1			T1	359		T3	8		T9	57
valid_sources[0x66]	414835	1			T1	351		T3	10		T9	69
valid_sources[0x67]	412655	1			T1	330		T3	5		T9	52
valid_sources[0x68]	1178766	1			T1	353		T3	7		T9	58
valid_sources[0x69]	413349	1			T1	356		T3	7		T9	44
valid_sources[0x6a]	416565	1			T1	341		T3	4		T9	69
valid_sources[0x6b]	414945	1			T1	366		T3	5		T9	57
valid_sources[0x6c]	415894	1			T1	333		T3	4		T9	78
valid_sources[0x6d]	412158	1			T1	318		T3	4		T9	58
valid_sources[0x6e]	417720	1			T1	347		T3	4		T9	61
valid_sources[0x6f]	413419	1			T1	359		T3	5		T9	58
valid_sources[0x70]	418223	1			T1	337		T3	4		T9	65
valid_sources[0x71]	559995	1			T1	365		T3	3		T9	38
valid_sources[0x72]	416743	1			T1	316		T3	3		T9	53
valid_sources[0x73]	414051	1			T1	382		T3	4		T9	37
valid_sources[0x74]	412975	1			T1	352		T3	2		T9	68
valid_sources[0x75]	418735	1			T1	338		T3	9		T9	65
valid_sources[0x76]	415883	1			T1	361		T3	5		T9	62
valid_sources[0x77]	415008	1			T1	334		T3	6		T9	54
valid_sources[0x78]	1336615	1			T1	347		T3	5		T9	58
valid_sources[0x79]	416011	1			T1	387		T3	7		T9	61
valid_sources[0x7a]	416169	1			T1	347		T3	8		T9	77
valid_sources[0x7b]	417800	1			T1	372		T3	4		T9	45
valid_sources[0x7c]	716859	1			T1	381		T3	3		T9	45
valid_sources[0x7d]	1717944	1			T1	347		T3	3		T9	49
valid_sources[0x7e]	2010417	1			T1	365		T3	7		T9	62
valid_sources[0x7f]	5137322	1			T1	298		T3	6		T9	47
valid_sources[0x80]	413494	1			T1	329		T3	7		T9	53

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72621269

1

T1

44183

T3

721

T5

1

values[0x0]

all_enables

biggest_size

62677

1

T1

22

T3

5

T8

2

values[0x1]

all_enables

biggest_size

60762

1

T1

18

T3

5

T8

2