Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	170710	0	0
cfg0_rd_A	2147483647	1159	0	0
compare_lower0_0_rd_A	2147483647	934	0	0
compare_upper0_0_rd_A	2147483647	958	0	0
ctrl_rd_A	2147483647	943	0	0
intr_enable0_rd_A	2147483647	1944	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	170710	0	0
T9	352620	15173	0	0
T10	939732	0	0	0
T12	0	26398	0	0
T13	898013	0	0	0
T14	0	29029	0	0
T18	187962	0	0	0
T21	12506	0	0	0
T22	891802	0	0	0
T23	339158	0	0	0
T24	0	5122	0	0
T25	0	12853	0	0
T26	0	3939	0	0
T27	0	12244	0	0
T28	0	7770	0	0
T29	0	12160	0	0
T30	0	5015	0	0
T31	24067	0	0	0
T32	202381	0	0	0
T33	718751	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1159	0	0
T28	245741	42	0	0
T34	0	47	0	0
T35	0	20	0	0
T36	0	120	0	0
T37	0	43	0	0
T38	0	40	0	0
T39	0	119	0	0
T40	0	11	0	0
T41	0	116	0	0
T42	0	24	0	0
T43	106941	0	0	0
T44	495036	0	0	0
T45	537451	0	0	0
T46	931734	0	0	0
T47	128111	0	0	0
T48	345506	0	0	0
T49	145738	0	0	0
T50	238368	0	0	0
T51	652715	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	934	0	0
T28	245741	26	0	0
T34	0	23	0	0
T35	0	27	0	0
T36	0	131	0	0
T37	0	52	0	0
T38	0	36	0	0
T39	0	66	0	0
T40	0	13	0	0
T41	0	113	0	0
T42	0	19	0	0
T43	106941	0	0	0
T44	495036	0	0	0
T45	537451	0	0	0
T46	931734	0	0	0
T47	128111	0	0	0
T48	345506	0	0	0
T49	145738	0	0	0
T50	238368	0	0	0
T51	652715	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	958	0	0
T28	245741	37	0	0
T34	0	25	0	0
T35	0	34	0	0
T36	0	116	0	0
T37	0	18	0	0
T38	0	43	0	0
T39	0	82	0	0
T40	0	4	0	0
T41	0	120	0	0
T42	0	6	0	0
T43	106941	0	0	0
T44	495036	0	0	0
T45	537451	0	0	0
T46	931734	0	0	0
T47	128111	0	0	0
T48	345506	0	0	0
T49	145738	0	0	0
T50	238368	0	0	0
T51	652715	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	943	0	0
T28	245741	76	0	0
T34	0	19	0	0
T35	0	12	0	0
T36	0	129	0	0
T37	0	23	0	0
T38	0	9	0	0
T39	0	58	0	0
T40	0	19	0	0
T41	0	114	0	0
T42	0	10	0	0
T43	106941	0	0	0
T44	495036	0	0	0
T45	537451	0	0	0
T46	931734	0	0	0
T47	128111	0	0	0
T48	345506	0	0	0
T49	145738	0	0	0
T50	238368	0	0	0
T51	652715	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1944	0	0
T11	950550	30	0	0
T28	0	144	0	0
T52	0	50	0	0
T53	0	43	0	0
T54	0	28	0	0
T55	0	11	0	0
T56	0	50	0	0
T57	0	59	0	0
T58	0	63	0	0
T59	0	16	0	0
T60	137407	0	0	0
T61	208281	0	0	0
T62	900532	0	0	0
T63	796101	0	0	0
T64	545915	0	0	0
T65	167687	0	0	0
T66	122918	0	0	0
T67	104911	0	0	0
T68	27067	0	0	0