Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66813074	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

66952008

1

T1

106

T2

1

T5

408

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	133634611	1			T1	192		T2	1		T3	1
values[0x0]	63043	1			T1	7		T5	31		T6	4
values[0x1]	67428	1			T1	3		T5	15		T6	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53391594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

80373488

1

T1

122

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	394348	1			T6	32		T11	25		T16	91
valid_sources[0x01]	393143	1			T1	4		T6	38		T11	23
valid_sources[0x02]	484868	1			T6	35		T11	18		T16	113
valid_sources[0x03]	392460	1			T6	44		T11	20		T16	72
valid_sources[0x04]	764980	1			T6	26		T11	27		T16	77
valid_sources[0x05]	2259955	1			T6	35		T11	25		T16	86
valid_sources[0x06]	393975	1			T6	35		T11	21		T16	86
valid_sources[0x07]	1534393	1			T6	43		T11	28		T16	81
valid_sources[0x08]	402050	1			T6	39		T11	19		T16	81
valid_sources[0x09]	391454	1			T6	36		T11	24		T16	96
valid_sources[0x0a]	390683	1			T1	1		T6	55		T11	19
valid_sources[0x0b]	392997	1			T6	40		T11	28		T16	83
valid_sources[0x0c]	401144	1			T6	25		T10	6614		T11	21
valid_sources[0x0d]	392899	1			T6	62		T11	28		T16	83
valid_sources[0x0e]	393162	1			T6	26		T11	15		T16	102
valid_sources[0x0f]	436442	1			T6	44		T11	28		T16	106
valid_sources[0x10]	390712	1			T6	50		T11	30		T16	97
valid_sources[0x11]	389018	1			T1	1		T6	41		T11	26
valid_sources[0x12]	438433	1			T6	69		T11	18		T16	106
valid_sources[0x13]	396115	1			T6	45		T11	22		T16	82
valid_sources[0x14]	390756	1			T6	57		T11	22		T16	90
valid_sources[0x15]	393167	1			T6	53		T11	20		T16	72
valid_sources[0x16]	392666	1			T1	1		T6	45		T11	23
valid_sources[0x17]	391876	1			T6	60		T11	27		T16	101
valid_sources[0x18]	393083	1			T6	36		T11	23		T16	93
valid_sources[0x19]	3540211	1			T6	50		T11	24		T16	97
valid_sources[0x1a]	394977	1			T6	46		T11	22		T16	89
valid_sources[0x1b]	392777	1			T6	39		T11	29		T16	92
valid_sources[0x1c]	390876	1			T6	39		T11	32		T16	93
valid_sources[0x1d]	392801	1			T4	1		T6	46		T11	29
valid_sources[0x1e]	391082	1			T6	53		T11	22		T16	102
valid_sources[0x1f]	392629	1			T6	41		T11	18		T16	78
valid_sources[0x20]	1142966	1			T1	1		T6	35		T11	25
valid_sources[0x21]	392430	1			T6	47		T11	13		T16	107
valid_sources[0x22]	393403	1			T1	1		T6	62		T11	25
valid_sources[0x23]	391174	1			T1	2		T6	29		T11	20
valid_sources[0x24]	395255	1			T6	34		T11	17		T16	94
valid_sources[0x25]	396525	1			T6	42		T11	24		T16	87
valid_sources[0x26]	395749	1			T1	4		T6	42		T11	25
valid_sources[0x27]	391077	1			T6	41		T11	22		T16	96
valid_sources[0x28]	397841	1			T6	41		T11	25		T16	102
valid_sources[0x29]	395524	1			T6	26		T11	30		T16	110
valid_sources[0x2a]	393183	1			T6	32		T11	18		T16	77
valid_sources[0x2b]	390474	1			T6	20		T11	38		T16	94
valid_sources[0x2c]	1364444	1			T6	48		T11	21		T16	86
valid_sources[0x2d]	403525	1			T6	30		T11	24		T16	90
valid_sources[0x2e]	392819	1			T6	37		T11	27		T16	84
valid_sources[0x2f]	393050	1			T6	49		T11	29		T16	96
valid_sources[0x30]	448328	1			T6	28		T11	33		T16	72
valid_sources[0x31]	395196	1			T6	24		T11	16		T16	94
valid_sources[0x32]	394883	1			T1	1		T6	40		T11	24
valid_sources[0x33]	398959	1			T6	27		T11	17		T16	124
valid_sources[0x34]	393681	1			T1	2		T6	34		T11	15
valid_sources[0x35]	388503	1			T1	3		T6	21		T11	18
valid_sources[0x36]	392834	1			T6	51		T11	25		T16	101
valid_sources[0x37]	391713	1			T1	2		T6	33		T11	16
valid_sources[0x38]	393277	1			T6	37		T11	23		T16	96
valid_sources[0x39]	394753	1			T6	38		T11	22		T16	80
valid_sources[0x3a]	394221	1			T6	51		T11	17		T16	106
valid_sources[0x3b]	390307	1			T6	33		T11	20		T16	106
valid_sources[0x3c]	391062	1			T6	50		T11	28		T16	85
valid_sources[0x3d]	394073	1			T6	48		T11	26		T16	85
valid_sources[0x3e]	391979	1			T1	4		T6	37		T11	21
valid_sources[0x3f]	391203	1			T6	30		T11	20		T16	86
valid_sources[0x40]	390953	1			T1	13		T3	1		T6	30
valid_sources[0x41]	393051	1			T6	45		T11	26		T16	91
valid_sources[0x42]	922848	1			T6	51		T11	22		T16	71
valid_sources[0x43]	424810	1			T6	32		T11	20		T16	90
valid_sources[0x44]	391213	1			T1	1		T6	32		T11	24
valid_sources[0x45]	392989	1			T6	38		T11	22		T16	101
valid_sources[0x46]	389351	1			T6	31		T11	21		T16	79
valid_sources[0x47]	393635	1			T6	50		T11	30		T16	72
valid_sources[0x48]	2316246	1			T6	36		T11	21		T16	95
valid_sources[0x49]	425297	1			T6	50		T11	24		T16	98
valid_sources[0x4a]	390849	1			T1	4		T6	71		T11	15
valid_sources[0x4b]	396871	1			T1	4		T6	45		T11	30
valid_sources[0x4c]	391364	1			T6	33		T11	11		T16	89
valid_sources[0x4d]	390441	1			T1	1		T6	54		T11	13
valid_sources[0x4e]	394082	1			T6	26		T11	14		T16	89
valid_sources[0x4f]	394256	1			T6	28		T11	24		T16	87
valid_sources[0x50]	396787	1			T6	41		T11	25		T16	81
valid_sources[0x51]	393484	1			T6	57		T11	18		T16	107
valid_sources[0x52]	395351	1			T6	44		T11	20		T16	96
valid_sources[0x53]	652087	1			T6	28		T11	30		T16	74
valid_sources[0x54]	432053	1			T6	51		T11	36		T16	88
valid_sources[0x55]	740757	1			T1	1		T6	57		T11	27
valid_sources[0x56]	406746	1			T6	40		T11	16		T16	89
valid_sources[0x57]	392359	1			T6	35		T11	28		T16	87
valid_sources[0x58]	393081	1			T6	29		T11	23		T16	97
valid_sources[0x59]	4233242	1			T6	41		T11	21		T16	67
valid_sources[0x5a]	395411	1			T6	31		T11	26		T16	90
valid_sources[0x5b]	390842	1			T6	21		T11	23		T16	89
valid_sources[0x5c]	407472	1			T1	2		T6	42		T11	19
valid_sources[0x5d]	394645	1			T6	33		T11	28		T16	82
valid_sources[0x5e]	390280	1			T1	6		T6	40		T11	23
valid_sources[0x5f]	959371	1			T6	34		T11	22		T16	70
valid_sources[0x60]	393974	1			T6	34		T11	21		T16	91
valid_sources[0x61]	395644	1			T2	1		T6	47		T11	29
valid_sources[0x62]	514046	1			T6	39		T11	23		T16	97
valid_sources[0x63]	390432	1			T6	32		T11	24		T16	97
valid_sources[0x64]	389834	1			T6	27		T11	19		T16	94
valid_sources[0x65]	393508	1			T6	27		T11	27		T16	87
valid_sources[0x66]	395440	1			T6	56		T11	26		T16	99
valid_sources[0x67]	391329	1			T6	36		T11	19		T16	87
valid_sources[0x68]	402507	1			T6	51		T11	15		T16	81
valid_sources[0x69]	393722	1			T6	57		T11	23		T16	101
valid_sources[0x6a]	390270	1			T6	45		T11	19		T16	100
valid_sources[0x6b]	416081	1			T6	28		T11	17		T16	101
valid_sources[0x6c]	402146	1			T6	56		T11	29		T16	87
valid_sources[0x6d]	428541	1			T6	28		T11	25		T16	86
valid_sources[0x6e]	396426	1			T1	1		T6	43		T11	29
valid_sources[0x6f]	864734	1			T6	31		T11	34		T16	86
valid_sources[0x70]	393800	1			T1	4		T6	46		T11	23
valid_sources[0x71]	391655	1			T6	30		T11	28		T16	99
valid_sources[0x72]	392562	1			T1	1		T6	43		T11	28
valid_sources[0x73]	389421	1			T6	70		T11	22		T16	121
valid_sources[0x74]	390758	1			T6	33		T11	19		T16	88
valid_sources[0x75]	393387	1			T6	24		T11	15		T16	87
valid_sources[0x76]	392597	1			T6	31		T11	26		T16	93
valid_sources[0x77]	392581	1			T6	35		T11	26		T16	97
valid_sources[0x78]	389404	1			T6	31		T11	21		T16	102
valid_sources[0x79]	427289	1			T6	21		T11	18		T16	86
valid_sources[0x7a]	397388	1			T6	47		T11	20		T16	85
valid_sources[0x7b]	444528	1			T6	55		T11	15		T16	104
valid_sources[0x7c]	389653	1			T1	1		T6	26		T11	21
valid_sources[0x7d]	553189	1			T6	32		T11	23		T16	94
valid_sources[0x7e]	391329	1			T6	51		T11	25		T16	79
valid_sources[0x7f]	396717	1			T1	2		T6	32		T11	17
valid_sources[0x80]	394158	1			T6	22		T11	27		T16	97

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66838331

1

T1

100

T2

1

T5

376

values[0x0]

all_enables

biggest_size

57638

1

T1

4

T5

24

T6

3

values[0x1]

all_enables

biggest_size

56039

1

T1

2

T5

8

T6

3