Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	151367	0	0
cfg0_rd_A	2147483647	2171	0	0
compare_lower0_0_rd_A	2147483647	2363	0	0
compare_upper0_0_rd_A	2147483647	2051	0	0
ctrl_rd_A	2147483647	2055	0	0
intr_enable0_rd_A	2147483647	3398	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	151367	0	0
T11	181863	5151	0	0
T12	200136	9803	0	0
T13	211868	0	0	0
T14	193514	0	0	0
T15	10493	472	0	0
T16	379775	0	0	0
T17	161480	0	0	0
T18	1889	0	0	0
T24	0	10209	0	0
T25	251838	0	0	0
T26	0	6376	0	0
T27	0	3292	0	0
T28	0	15076	0	0
T29	0	17323	0	0
T30	0	3181	0	0
T31	0	4684	0	0
T32	676201	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2171	0	0
T11	181863	17	0	0
T12	200136	0	0	0
T13	211868	0	0	0
T14	193514	0	0	0
T15	10493	24	0	0
T16	379775	0	0	0
T17	161480	0	0	0
T18	1889	0	0	0
T23	0	7	0	0
T24	0	53	0	0
T25	251838	0	0	0
T26	0	54	0	0
T27	0	57	0	0
T31	0	82	0	0
T32	676201	0	0	0
T33	0	137	0	0
T34	0	60	0	0
T35	0	37	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2363	0	0
T11	181863	42	0	0
T12	200136	0	0	0
T13	211868	0	0	0
T14	193514	0	0	0
T15	10493	22	0	0
T16	379775	0	0	0
T17	161480	0	0	0
T18	1889	0	0	0
T23	0	6	0	0
T24	0	70	0	0
T25	251838	0	0	0
T26	0	91	0	0
T27	0	57	0	0
T31	0	95	0	0
T32	676201	0	0	0
T33	0	150	0	0
T34	0	90	0	0
T35	0	75	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2051	0	0
T11	181863	36	0	0
T12	200136	0	0	0
T13	211868	0	0	0
T14	193514	0	0	0
T15	10493	11	0	0
T16	379775	0	0	0
T17	161480	0	0	0
T18	1889	0	0	0
T23	0	4	0	0
T24	0	74	0	0
T25	251838	0	0	0
T26	0	87	0	0
T27	0	61	0	0
T31	0	41	0	0
T32	676201	0	0	0
T33	0	142	0	0
T34	0	80	0	0
T35	0	39	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2055	0	0
T11	181863	49	0	0
T12	200136	0	0	0
T13	211868	0	0	0
T14	193514	0	0	0
T15	10493	15	0	0
T16	379775	0	0	0
T17	161480	0	0	0
T18	1889	0	0	0
T23	0	7	0	0
T24	0	42	0	0
T25	251838	0	0	0
T26	0	100	0	0
T27	0	46	0	0
T31	0	68	0	0
T32	676201	0	0	0
T33	0	106	0	0
T34	0	100	0	0
T35	0	39	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3398	0	0
T11	181863	64	0	0
T12	200136	0	0	0
T13	211868	0	0	0
T14	193514	0	0	0
T15	10493	24	0	0
T16	379775	0	0	0
T17	161480	0	0	0
T18	1889	0	0	0
T24	0	103	0	0
T25	251838	0	0	0
T26	0	151	0	0
T27	0	157	0	0
T31	0	137	0	0
T32	676201	0	0	0
T33	0	264	0	0
T36	0	52	0	0
T37	0	32	0	0
T38	0	29	0	0