| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.67 | 99.33 | 99.04 | 100.00 | 100.00 | 100.00 | 99.66 |
| T56 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.3070678299 | Sep 24 05:58:15 AM UTC 24 | Sep 24 05:58:17 AM UTC 24 | 18216045 ps | ||
| T505 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4056867030 | Sep 24 05:58:15 AM UTC 24 | Sep 24 05:58:17 AM UTC 24 | 195851717 ps | ||
| T506 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2813656913 | Sep 24 05:58:15 AM UTC 24 | Sep 24 05:58:17 AM UTC 24 | 150042643 ps | ||
| T507 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.127548582 | Sep 24 05:58:16 AM UTC 24 | Sep 24 05:58:19 AM UTC 24 | 107656023 ps | ||
| T508 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.771962447 | Sep 24 05:58:16 AM UTC 24 | Sep 24 05:58:19 AM UTC 24 | 50515556 ps | ||
| T509 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.3705832881 | Sep 24 05:58:14 AM UTC 24 | Sep 24 05:58:19 AM UTC 24 | 184460418 ps | ||
| T510 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.1586714471 | Sep 24 05:58:18 AM UTC 24 | Sep 24 05:58:20 AM UTC 24 | 13503824 ps | ||
| T511 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.1009789542 | Sep 24 05:58:18 AM UTC 24 | Sep 24 05:58:20 AM UTC 24 | 28789325 ps | ||
| T512 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1913421720 | Sep 24 05:58:18 AM UTC 24 | Sep 24 05:58:20 AM UTC 24 | 46002085 ps | ||
| T513 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1971398203 | Sep 24 05:58:18 AM UTC 24 | Sep 24 05:58:20 AM UTC 24 | 273724404 ps | ||
| T514 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2124455160 | Sep 24 05:58:19 AM UTC 24 | Sep 24 05:58:22 AM UTC 24 | 117726127 ps | ||
| T515 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.3033414767 | Sep 24 05:58:19 AM UTC 24 | Sep 24 05:58:22 AM UTC 24 | 80845768 ps | ||
| T516 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.251653736 | Sep 24 05:58:20 AM UTC 24 | Sep 24 05:58:22 AM UTC 24 | 15475928 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1157927179 | Sep 24 05:58:21 AM UTC 24 | Sep 24 05:58:23 AM UTC 24 | 22376155 ps | ||
| T517 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2426518180 | Sep 24 05:58:21 AM UTC 24 | Sep 24 05:58:23 AM UTC 24 | 37823539 ps | ||
| T518 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.723834304 | Sep 24 05:58:21 AM UTC 24 | Sep 24 05:58:23 AM UTC 24 | 59645158 ps | ||
| T519 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.911422171 | Sep 24 05:58:20 AM UTC 24 | Sep 24 05:58:23 AM UTC 24 | 39432603 ps | ||
| T520 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3498038143 | Sep 24 05:58:22 AM UTC 24 | Sep 24 05:58:25 AM UTC 24 | 69349270 ps | ||
| T521 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.231693060 | Sep 24 05:58:23 AM UTC 24 | Sep 24 05:58:25 AM UTC 24 | 30785252 ps | ||
| T522 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2123923780 | Sep 24 05:58:23 AM UTC 24 | Sep 24 05:58:25 AM UTC 24 | 14133565 ps | ||
| T523 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.3097168521 | Sep 24 05:58:21 AM UTC 24 | Sep 24 05:58:25 AM UTC 24 | 112536827 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.2547540296 | Sep 24 05:58:23 AM UTC 24 | Sep 24 05:58:25 AM UTC 24 | 22754655 ps | ||
| T524 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3410112411 | Sep 24 05:58:23 AM UTC 24 | Sep 24 05:58:26 AM UTC 24 | 21250419 ps | ||
| T525 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3026354039 | Sep 24 05:58:23 AM UTC 24 | Sep 24 05:58:26 AM UTC 24 | 309641674 ps | ||
| T526 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.510292056 | Sep 24 05:58:25 AM UTC 24 | Sep 24 05:58:26 AM UTC 24 | 13316106 ps | ||
| T527 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.2940776657 | Sep 24 05:58:25 AM UTC 24 | Sep 24 05:58:27 AM UTC 24 | 26004552 ps | ||
| T528 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.92178928 | Sep 24 05:58:23 AM UTC 24 | Sep 24 05:58:27 AM UTC 24 | 269378985 ps | ||
| T529 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.3212716551 | Sep 24 05:58:26 AM UTC 24 | Sep 24 05:58:28 AM UTC 24 | 13764250 ps | ||
| T530 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2293540435 | Sep 24 05:58:26 AM UTC 24 | Sep 24 05:58:29 AM UTC 24 | 61195035 ps | ||
| T531 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2312989537 | Sep 24 05:58:26 AM UTC 24 | Sep 24 05:58:29 AM UTC 24 | 32414348 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3018572449 | Sep 24 05:58:26 AM UTC 24 | Sep 24 05:58:29 AM UTC 24 | 149654093 ps | ||
| T532 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.3441563699 | Sep 24 05:58:28 AM UTC 24 | Sep 24 05:58:30 AM UTC 24 | 36769229 ps | ||
| T533 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2577227353 | Sep 24 05:58:28 AM UTC 24 | Sep 24 05:58:30 AM UTC 24 | 49216647 ps | ||
| T534 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1690441712 | Sep 24 05:58:28 AM UTC 24 | Sep 24 05:58:30 AM UTC 24 | 56113260 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.3307149369 | Sep 24 05:58:26 AM UTC 24 | Sep 24 05:58:30 AM UTC 24 | 170942103 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.2112170026 | Sep 24 05:58:29 AM UTC 24 | Sep 24 05:58:31 AM UTC 24 | 197471144 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.1341074781 | Sep 24 05:58:28 AM UTC 24 | Sep 24 05:58:31 AM UTC 24 | 83919494 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.3696692646 | Sep 24 05:58:29 AM UTC 24 | Sep 24 05:58:31 AM UTC 24 | 40668019 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1551588512 | Sep 24 05:58:28 AM UTC 24 | Sep 24 05:58:31 AM UTC 24 | 175516970 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3322551857 | Sep 24 05:58:29 AM UTC 24 | Sep 24 05:58:31 AM UTC 24 | 99240187 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1444224412 | Sep 24 05:58:29 AM UTC 24 | Sep 24 05:58:32 AM UTC 24 | 19197293 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.4185202157 | Sep 24 05:58:31 AM UTC 24 | Sep 24 05:58:33 AM UTC 24 | 35291250 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.1508715436 | Sep 24 05:58:31 AM UTC 24 | Sep 24 05:58:33 AM UTC 24 | 13386606 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.2915528215 | Sep 24 05:58:31 AM UTC 24 | Sep 24 05:58:33 AM UTC 24 | 207845227 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2600640533 | Sep 24 05:58:31 AM UTC 24 | Sep 24 05:58:34 AM UTC 24 | 114221516 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.1506204901 | Sep 24 05:58:33 AM UTC 24 | Sep 24 05:58:34 AM UTC 24 | 45525545 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.1163495091 | Sep 24 05:58:32 AM UTC 24 | Sep 24 05:58:34 AM UTC 24 | 22249171 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.403415799 | Sep 24 05:58:33 AM UTC 24 | Sep 24 05:58:34 AM UTC 24 | 81815815 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.660015445 | Sep 24 05:58:33 AM UTC 24 | Sep 24 05:58:34 AM UTC 24 | 28162467 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1269820936 | Sep 24 05:58:32 AM UTC 24 | Sep 24 05:58:34 AM UTC 24 | 54237488 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3084089242 | Sep 24 05:58:32 AM UTC 24 | Sep 24 05:58:35 AM UTC 24 | 156297662 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.149554994 | Sep 24 05:58:34 AM UTC 24 | Sep 24 05:58:36 AM UTC 24 | 21468854 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1602183770 | Sep 24 05:58:34 AM UTC 24 | Sep 24 05:58:36 AM UTC 24 | 27385940 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.559349551 | Sep 24 05:58:34 AM UTC 24 | Sep 24 05:58:36 AM UTC 24 | 15085984 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.2161530945 | Sep 24 05:58:35 AM UTC 24 | Sep 24 05:58:37 AM UTC 24 | 27173717 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.3653076145 | Sep 24 05:58:35 AM UTC 24 | Sep 24 05:58:37 AM UTC 24 | 70850292 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.4189409444 | Sep 24 05:58:36 AM UTC 24 | Sep 24 05:58:37 AM UTC 24 | 12758671 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.2879413030 | Sep 24 05:58:36 AM UTC 24 | Sep 24 05:58:37 AM UTC 24 | 31412628 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.2078746176 | Sep 24 05:58:36 AM UTC 24 | Sep 24 05:58:38 AM UTC 24 | 14083027 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.3290422590 | Sep 24 05:58:36 AM UTC 24 | Sep 24 05:58:38 AM UTC 24 | 16753020 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.194648347 | Sep 24 05:58:37 AM UTC 24 | Sep 24 05:58:39 AM UTC 24 | 34208979 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.1921988863 | Sep 24 05:58:37 AM UTC 24 | Sep 24 05:58:39 AM UTC 24 | 16191051 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.2901659717 | Sep 24 05:58:37 AM UTC 24 | Sep 24 05:58:39 AM UTC 24 | 44094645 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.4114161700 | Sep 24 05:58:37 AM UTC 24 | Sep 24 05:58:39 AM UTC 24 | 10848328 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.375266844 | Sep 24 05:58:37 AM UTC 24 | Sep 24 05:58:39 AM UTC 24 | 44369862 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.2593193058 | Sep 24 05:58:39 AM UTC 24 | Sep 24 05:58:41 AM UTC 24 | 13953923 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.197516301 | Sep 24 05:58:39 AM UTC 24 | Sep 24 05:58:41 AM UTC 24 | 18243282 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2412381681 | Sep 24 05:58:39 AM UTC 24 | Sep 24 05:58:41 AM UTC 24 | 116918278 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.3963156223 | Sep 24 05:58:39 AM UTC 24 | Sep 24 05:58:41 AM UTC 24 | 11393169 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.3955655837 | Sep 24 05:58:39 AM UTC 24 | Sep 24 05:58:41 AM UTC 24 | 17594109 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.4074129590 | Sep 24 05:58:39 AM UTC 24 | Sep 24 05:58:41 AM UTC 24 | 24568354 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.3121015267 | Sep 24 05:58:41 AM UTC 24 | Sep 24 05:58:42 AM UTC 24 | 35459342 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.3422515852 | Sep 24 05:58:41 AM UTC 24 | Sep 24 05:58:42 AM UTC 24 | 30071636 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.2078838930 | Sep 24 05:58:40 AM UTC 24 | Sep 24 05:58:42 AM UTC 24 | 16475711 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.3836789644 | Sep 24 05:58:41 AM UTC 24 | Sep 24 05:58:42 AM UTC 24 | 14996035 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.4120189911 | Sep 24 05:58:41 AM UTC 24 | Sep 24 05:58:42 AM UTC 24 | 42216625 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.4071116356 | Sep 24 05:58:42 AM UTC 24 | Sep 24 05:58:44 AM UTC 24 | 16185026 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.246113719 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 43933555730 ps |
| CPU time | 91.36 seconds |
| Started | Sep 24 05:12:38 AM UTC 24 |
| Finished | Sep 24 05:14:12 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246113719 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.246113719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all_with_rand_reset.3372992729 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7274562167 ps |
| CPU time | 27.57 seconds |
| Started | Sep 24 05:13:45 AM UTC 24 |
| Finished | Sep 24 05:14:14 AM UTC 24 |
| Peak memory | 205232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3372992729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.rv_timer_stress_all_with_rand_reset.3372992729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1227905389 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 134286179 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 05:57:17 AM UTC 24 |
| Finished | Sep 24 05:57:19 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227905389 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.1227905389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.2194991006 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 748182656286 ps |
| CPU time | 198.1 seconds |
| Started | Sep 24 05:12:49 AM UTC 24 |
| Finished | Sep 24 05:16:11 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194991006 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2194991006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.589149325 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2732908812759 ps |
| CPU time | 4835.41 seconds |
| Started | Sep 24 05:32:44 AM UTC 24 |
| Finished | Sep 24 06:54:11 AM UTC 24 |
| Peak memory | 202640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589149325 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.589149325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/44.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.1610525854 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2489405560819 ps |
| CPU time | 3582.06 seconds |
| Started | Sep 24 05:36:05 AM UTC 24 |
| Finished | Sep 24 06:36:27 AM UTC 24 |
| Peak memory | 202636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610525854 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.1610525854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/49.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.617835428 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1282731719205 ps |
| CPU time | 1515.78 seconds |
| Started | Sep 24 05:18:34 AM UTC 24 |
| Finished | Sep 24 05:44:07 AM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617835428 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.617835428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/20.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.1611290928 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 576023930025 ps |
| CPU time | 2260.71 seconds |
| Started | Sep 24 05:23:12 AM UTC 24 |
| Finished | Sep 24 06:01:20 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611290928 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.1611290928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/29.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.307741786 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 488690087030 ps |
| CPU time | 517.32 seconds |
| Started | Sep 24 05:14:21 AM UTC 24 |
| Finished | Sep 24 05:23:05 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307741786 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.307741786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/6.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.359167672 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 121834780222 ps |
| CPU time | 504.49 seconds |
| Started | Sep 24 05:12:45 AM UTC 24 |
| Finished | Sep 24 05:21:17 AM UTC 24 |
| Peak memory | 201272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359167672 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.359167672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.3389667196 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2943806417364 ps |
| CPU time | 1552.51 seconds |
| Started | Sep 24 05:16:56 AM UTC 24 |
| Finished | Sep 24 05:43:05 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389667196 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.3389667196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/15.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.3158687863 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 91690761 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 05:57:37 AM UTC 24 |
| Finished | Sep 24 05:57:39 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158687863 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3158687863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.1111821398 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 844717649351 ps |
| CPU time | 3608.23 seconds |
| Started | Sep 24 05:16:50 AM UTC 24 |
| Finished | Sep 24 06:17:36 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111821398 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.1111821398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/14.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.1418796573 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4683563626568 ps |
| CPU time | 1927.73 seconds |
| Started | Sep 24 05:20:56 AM UTC 24 |
| Finished | Sep 24 05:53:26 AM UTC 24 |
| Peak memory | 202964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418796573 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.1418796573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/25.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.538078919 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 168953620767 ps |
| CPU time | 367.54 seconds |
| Started | Sep 24 05:22:04 AM UTC 24 |
| Finished | Sep 24 05:28:17 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538078919 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.538078919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/28.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.3023812162 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 969168448914 ps |
| CPU time | 1269.45 seconds |
| Started | Sep 24 05:31:56 AM UTC 24 |
| Finished | Sep 24 05:53:20 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023812162 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.3023812162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/43.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.3937711372 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 123218923279 ps |
| CPU time | 404.44 seconds |
| Started | Sep 24 05:12:57 AM UTC 24 |
| Finished | Sep 24 05:19:47 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937711372 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.3937711372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.1583958816 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 397857699933 ps |
| CPU time | 1047.3 seconds |
| Started | Sep 24 05:14:35 AM UTC 24 |
| Finished | Sep 24 05:32:16 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583958816 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1583958816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/8.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.1430894464 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 58494950 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 05:12:45 AM UTC 24 |
| Finished | Sep 24 05:12:47 AM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430894464 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1430894464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.3690129689 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1222580560534 ps |
| CPU time | 905.34 seconds |
| Started | Sep 24 05:22:02 AM UTC 24 |
| Finished | Sep 24 05:37:18 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690129689 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.3690129689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/27.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.2457561024 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1247763231338 ps |
| CPU time | 1751.9 seconds |
| Started | Sep 24 05:18:45 AM UTC 24 |
| Finished | Sep 24 05:48:17 AM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457561024 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.2457561024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/21.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.1656804123 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1524012600954 ps |
| CPU time | 5956.01 seconds |
| Started | Sep 24 05:27:16 AM UTC 24 |
| Finished | Sep 24 07:07:38 AM UTC 24 |
| Peak memory | 202708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656804123 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.1656804123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/36.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.3391785434 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 246354103931 ps |
| CPU time | 800.31 seconds |
| Started | Sep 24 05:21:40 AM UTC 24 |
| Finished | Sep 24 05:35:09 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391785434 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3391785434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/27.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.3494995451 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 223747411149 ps |
| CPU time | 648.11 seconds |
| Started | Sep 24 05:14:44 AM UTC 24 |
| Finished | Sep 24 05:25:39 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494995451 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3494995451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/9.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.4002155230 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 543876584534 ps |
| CPU time | 743.27 seconds |
| Started | Sep 24 05:13:01 AM UTC 24 |
| Finished | Sep 24 05:25:33 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002155230 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4002155230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.2281815768 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 773048979975 ps |
| CPU time | 2496.8 seconds |
| Started | Sep 24 05:33:34 AM UTC 24 |
| Finished | Sep 24 06:15:38 AM UTC 24 |
| Peak memory | 202836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281815768 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.2281815768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/46.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.2021776382 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 969395118080 ps |
| CPU time | 674.98 seconds |
| Started | Sep 24 05:33:38 AM UTC 24 |
| Finished | Sep 24 05:45:01 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021776382 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2021776382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/47.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.2120324651 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 350597267392 ps |
| CPU time | 387.69 seconds |
| Started | Sep 24 05:54:15 AM UTC 24 |
| Finished | Sep 24 06:00:48 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120324651 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2120324651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/184.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.3746619870 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 185123742176 ps |
| CPU time | 589.11 seconds |
| Started | Sep 24 05:54:00 AM UTC 24 |
| Finished | Sep 24 06:03:57 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746619870 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3746619870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/181.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.2241493264 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 927292450304 ps |
| CPU time | 1876.05 seconds |
| Started | Sep 24 05:55:47 AM UTC 24 |
| Finished | Sep 24 06:27:24 AM UTC 24 |
| Peak memory | 202688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241493264 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2241493264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/193.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.2986876380 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 559633743651 ps |
| CPU time | 1202.43 seconds |
| Started | Sep 24 05:25:48 AM UTC 24 |
| Finished | Sep 24 05:46:05 AM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986876380 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.2986876380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/34.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.1194886496 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 319800734365 ps |
| CPU time | 739.76 seconds |
| Started | Sep 24 05:43:18 AM UTC 24 |
| Finished | Sep 24 05:55:47 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194886496 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1194886496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/102.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.796073691 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1191023770149 ps |
| CPU time | 514.56 seconds |
| Started | Sep 24 05:46:32 AM UTC 24 |
| Finished | Sep 24 05:55:13 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796073691 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.796073691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/122.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.2245491844 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 186254011398 ps |
| CPU time | 718.61 seconds |
| Started | Sep 24 05:49:12 AM UTC 24 |
| Finished | Sep 24 06:01:19 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245491844 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2245491844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/147.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.2048704040 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 189480316647 ps |
| CPU time | 587.97 seconds |
| Started | Sep 24 05:56:57 AM UTC 24 |
| Finished | Sep 24 06:06:52 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048704040 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2048704040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/199.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.3262185971 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 213170542615 ps |
| CPU time | 1936.44 seconds |
| Started | Sep 24 05:32:46 AM UTC 24 |
| Finished | Sep 24 06:05:25 AM UTC 24 |
| Peak memory | 203024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262185971 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3262185971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/45.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.1880959143 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 176181846689 ps |
| CPU time | 993.31 seconds |
| Started | Sep 24 05:48:01 AM UTC 24 |
| Finished | Sep 24 06:04:46 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880959143 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1880959143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/136.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.2157342978 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 401914750592 ps |
| CPU time | 1546.73 seconds |
| Started | Sep 24 05:17:12 AM UTC 24 |
| Finished | Sep 24 05:43:16 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157342978 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2157342978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/17.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.2041634221 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 210789166525 ps |
| CPU time | 2081.4 seconds |
| Started | Sep 24 05:52:59 AM UTC 24 |
| Finished | Sep 24 06:28:03 AM UTC 24 |
| Peak memory | 202764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041634221 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2041634221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/172.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.3502044400 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 683673205055 ps |
| CPU time | 1812.79 seconds |
| Started | Sep 24 05:19:17 AM UTC 24 |
| Finished | Sep 24 05:49:49 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502044400 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.3502044400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/22.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.2238340936 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1434158126752 ps |
| CPU time | 1251.82 seconds |
| Started | Sep 24 05:23:55 AM UTC 24 |
| Finished | Sep 24 05:45:01 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238340936 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.2238340936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/30.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.2890363881 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 46156632084 ps |
| CPU time | 143.36 seconds |
| Started | Sep 24 05:33:45 AM UTC 24 |
| Finished | Sep 24 05:36:11 AM UTC 24 |
| Peak memory | 201348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890363881 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.2890363881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.2879244931 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 127702693160 ps |
| CPU time | 225.5 seconds |
| Started | Sep 24 05:44:15 AM UTC 24 |
| Finished | Sep 24 05:48:03 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879244931 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2879244931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/108.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.2243168441 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 146839099641 ps |
| CPU time | 328.26 seconds |
| Started | Sep 24 05:47:53 AM UTC 24 |
| Finished | Sep 24 05:53:26 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243168441 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2243168441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/133.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.2900293929 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 110035796879 ps |
| CPU time | 225.46 seconds |
| Started | Sep 24 05:52:21 AM UTC 24 |
| Finished | Sep 24 05:56:10 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900293929 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2900293929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/167.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.3757386413 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 132401827443 ps |
| CPU time | 313.36 seconds |
| Started | Sep 24 05:55:04 AM UTC 24 |
| Finished | Sep 24 06:00:22 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757386413 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3757386413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/186.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.1619422157 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 625785158688 ps |
| CPU time | 1674.12 seconds |
| Started | Sep 24 05:22:36 AM UTC 24 |
| Finished | Sep 24 05:50:49 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619422157 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.1619422157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/28.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.1372828009 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 91448726526 ps |
| CPU time | 229.18 seconds |
| Started | Sep 24 05:25:08 AM UTC 24 |
| Finished | Sep 24 05:29:01 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372828009 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.1372828009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.2388055173 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 117925960396 ps |
| CPU time | 262.81 seconds |
| Started | Sep 24 05:13:31 AM UTC 24 |
| Finished | Sep 24 05:17:58 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388055173 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2388055173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.1410398060 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 536475958256 ps |
| CPU time | 329.24 seconds |
| Started | Sep 24 05:37:19 AM UTC 24 |
| Finished | Sep 24 05:42:53 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410398060 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1410398060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/62.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.1881063888 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 796805458165 ps |
| CPU time | 1038.83 seconds |
| Started | Sep 24 05:42:54 AM UTC 24 |
| Finished | Sep 24 06:00:26 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881063888 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1881063888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/95.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2031693119 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 388527874 ps |
| CPU time | 1.97 seconds |
| Started | Sep 24 05:57:34 AM UTC 24 |
| Finished | Sep 24 05:57:37 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031693119 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.2031693119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.2525828760 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 169474362101 ps |
| CPU time | 951.71 seconds |
| Started | Sep 24 05:46:06 AM UTC 24 |
| Finished | Sep 24 06:02:10 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525828760 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2525828760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/116.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.1402606645 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 344694449784 ps |
| CPU time | 163.59 seconds |
| Started | Sep 24 05:47:49 AM UTC 24 |
| Finished | Sep 24 05:50:35 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402606645 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1402606645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/132.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.955991183 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 269769660817 ps |
| CPU time | 351.71 seconds |
| Started | Sep 24 05:50:44 AM UTC 24 |
| Finished | Sep 24 05:56:41 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955991183 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.955991183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/157.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.1912963747 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 283331202674 ps |
| CPU time | 1324.57 seconds |
| Started | Sep 24 05:52:30 AM UTC 24 |
| Finished | Sep 24 06:14:50 AM UTC 24 |
| Peak memory | 202892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912963747 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1912963747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/169.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.994375351 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 276145196849 ps |
| CPU time | 234.16 seconds |
| Started | Sep 24 05:54:03 AM UTC 24 |
| Finished | Sep 24 05:58:01 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994375351 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.994375351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/183.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.3779859027 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 349434901626 ps |
| CPU time | 236.6 seconds |
| Started | Sep 24 05:55:47 AM UTC 24 |
| Finished | Sep 24 05:59:47 AM UTC 24 |
| Peak memory | 201008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779859027 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3779859027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/194.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.294106962 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 93275327085 ps |
| CPU time | 905.28 seconds |
| Started | Sep 24 05:39:57 AM UTC 24 |
| Finished | Sep 24 05:55:13 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294106962 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.294106962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/79.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4243456375 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 37384917 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 05:57:28 AM UTC 24 |
| Finished | Sep 24 05:57:30 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243456375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.4243456375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.2434077382 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 101730897322 ps |
| CPU time | 215.58 seconds |
| Started | Sep 24 05:12:50 AM UTC 24 |
| Finished | Sep 24 05:16:28 AM UTC 24 |
| Peak memory | 201316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434077382 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.2434077382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.2124305641 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 479828216425 ps |
| CPU time | 697.56 seconds |
| Started | Sep 24 05:43:17 AM UTC 24 |
| Finished | Sep 24 05:55:03 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124305641 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2124305641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/101.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.980713647 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 563569418329 ps |
| CPU time | 544.75 seconds |
| Started | Sep 24 05:45:02 AM UTC 24 |
| Finished | Sep 24 05:54:14 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980713647 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.980713647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/111.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.1428885258 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 235269081741 ps |
| CPU time | 364.16 seconds |
| Started | Sep 24 05:45:03 AM UTC 24 |
| Finished | Sep 24 05:51:13 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428885258 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1428885258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/112.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.147635065 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 3391528487469 ps |
| CPU time | 3335.53 seconds |
| Started | Sep 24 05:16:22 AM UTC 24 |
| Finished | Sep 24 06:12:34 AM UTC 24 |
| Peak memory | 202768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147635065 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.147635065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/12.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.4093301819 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 532276310459 ps |
| CPU time | 639.99 seconds |
| Started | Sep 24 05:46:48 AM UTC 24 |
| Finished | Sep 24 05:57:36 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093301819 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.4093301819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/124.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.378427489 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 330670557339 ps |
| CPU time | 1025.7 seconds |
| Started | Sep 24 05:16:38 AM UTC 24 |
| Finished | Sep 24 05:33:56 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378427489 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.378427489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/13.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.3356824892 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 72798956690 ps |
| CPU time | 163.27 seconds |
| Started | Sep 24 05:48:03 AM UTC 24 |
| Finished | Sep 24 05:50:49 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356824892 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3356824892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/138.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.34389436 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 510362789676 ps |
| CPU time | 445.96 seconds |
| Started | Sep 24 05:17:30 AM UTC 24 |
| Finished | Sep 24 05:25:02 AM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34389436 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.34389436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/18.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.1938099080 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 316323229468 ps |
| CPU time | 308.16 seconds |
| Started | Sep 24 05:55:14 AM UTC 24 |
| Finished | Sep 24 06:00:27 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938099080 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1938099080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/188.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.706621846 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 47096596141 ps |
| CPU time | 123.16 seconds |
| Started | Sep 24 05:20:43 AM UTC 24 |
| Finished | Sep 24 05:22:48 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706621846 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.706621846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/25.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.4110808205 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 325967015729 ps |
| CPU time | 675.66 seconds |
| Started | Sep 24 05:29:46 AM UTC 24 |
| Finished | Sep 24 05:41:09 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110808205 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.4110808205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.1938035636 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 95615736176 ps |
| CPU time | 341.8 seconds |
| Started | Sep 24 05:30:21 AM UTC 24 |
| Finished | Sep 24 05:36:08 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938035636 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1938035636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/41.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.1167606256 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 308070630169 ps |
| CPU time | 818.03 seconds |
| Started | Sep 24 05:31:25 AM UTC 24 |
| Finished | Sep 24 05:45:12 AM UTC 24 |
| Peak memory | 200988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167606256 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.1167606256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/42.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.2642749411 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 359855944709 ps |
| CPU time | 164.11 seconds |
| Started | Sep 24 05:37:07 AM UTC 24 |
| Finished | Sep 24 05:39:56 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642749411 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2642749411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/58.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.1350346972 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 118930138566 ps |
| CPU time | 608.65 seconds |
| Started | Sep 24 05:38:31 AM UTC 24 |
| Finished | Sep 24 05:48:48 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350346972 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1350346972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/72.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.3533857018 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1427455366898 ps |
| CPU time | 424.24 seconds |
| Started | Sep 24 05:14:39 AM UTC 24 |
| Finished | Sep 24 05:21:49 AM UTC 24 |
| Peak memory | 200988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533857018 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.3533857018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.2480272356 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 454619395704 ps |
| CPU time | 1127.49 seconds |
| Started | Sep 24 05:12:40 AM UTC 24 |
| Finished | Sep 24 05:31:40 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480272356 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.2480272356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.300200509 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1134868881869 ps |
| CPU time | 402.64 seconds |
| Started | Sep 24 05:45:13 AM UTC 24 |
| Finished | Sep 24 05:52:02 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300200509 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.300200509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/114.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.597438943 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 67558848554 ps |
| CPU time | 103.64 seconds |
| Started | Sep 24 05:16:23 AM UTC 24 |
| Finished | Sep 24 05:18:11 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597438943 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.597438943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/13.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.824073837 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 49783843862 ps |
| CPU time | 107.68 seconds |
| Started | Sep 24 05:16:32 AM UTC 24 |
| Finished | Sep 24 05:18:21 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824073837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.824073837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/13.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.3316609060 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 159329806557 ps |
| CPU time | 134.12 seconds |
| Started | Sep 24 05:16:41 AM UTC 24 |
| Finished | Sep 24 05:18:58 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316609060 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.3316609060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.2647071912 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1265549824011 ps |
| CPU time | 676.9 seconds |
| Started | Sep 24 05:48:20 AM UTC 24 |
| Finished | Sep 24 05:59:45 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647071912 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2647071912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/141.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.268658459 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 108870000741 ps |
| CPU time | 562.63 seconds |
| Started | Sep 24 05:48:49 AM UTC 24 |
| Finished | Sep 24 05:58:19 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268658459 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.268658459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/144.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.1349691463 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 75733530228 ps |
| CPU time | 315.02 seconds |
| Started | Sep 24 05:50:11 AM UTC 24 |
| Finished | Sep 24 05:55:31 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349691463 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1349691463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/152.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.3571134567 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 169105413477 ps |
| CPU time | 517.58 seconds |
| Started | Sep 24 05:51:11 AM UTC 24 |
| Finished | Sep 24 05:59:55 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571134567 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3571134567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/162.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.3325853177 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 114046333327 ps |
| CPU time | 210.37 seconds |
| Started | Sep 24 05:53:13 AM UTC 24 |
| Finished | Sep 24 05:56:47 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325853177 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3325853177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/173.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.2163216106 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 47549697307 ps |
| CPU time | 1839.09 seconds |
| Started | Sep 24 05:53:27 AM UTC 24 |
| Finished | Sep 24 06:24:27 AM UTC 24 |
| Peak memory | 202688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163216106 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2163216106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/176.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.3317118624 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 169812360477 ps |
| CPU time | 333.3 seconds |
| Started | Sep 24 05:17:34 AM UTC 24 |
| Finished | Sep 24 05:23:12 AM UTC 24 |
| Peak memory | 201196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317118624 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.3317118624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.2449741168 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 633583915351 ps |
| CPU time | 617.3 seconds |
| Started | Sep 24 05:54:02 AM UTC 24 |
| Finished | Sep 24 06:04:27 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449741168 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2449741168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/182.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.2327507227 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 214164239129 ps |
| CPU time | 593.49 seconds |
| Started | Sep 24 05:55:44 AM UTC 24 |
| Finished | Sep 24 06:05:45 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327507227 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2327507227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/191.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.2943103391 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 29283528043 ps |
| CPU time | 1105.06 seconds |
| Started | Sep 24 05:19:04 AM UTC 24 |
| Finished | Sep 24 05:37:43 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943103391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2943103391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/22.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.1459382800 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2059379054207 ps |
| CPU time | 2120.4 seconds |
| Started | Sep 24 05:20:01 AM UTC 24 |
| Finished | Sep 24 05:55:46 AM UTC 24 |
| Peak memory | 203024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459382800 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.1459382800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/23.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.1232577757 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 241033575129 ps |
| CPU time | 421.64 seconds |
| Started | Sep 24 05:20:10 AM UTC 24 |
| Finished | Sep 24 05:27:17 AM UTC 24 |
| Peak memory | 201260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232577757 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.1232577757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.3957187681 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 110977054821 ps |
| CPU time | 1600.08 seconds |
| Started | Sep 24 05:30:43 AM UTC 24 |
| Finished | Sep 24 05:57:42 AM UTC 24 |
| Peak memory | 203032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957187681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3957187681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/41.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.593183847 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 185737812950 ps |
| CPU time | 156.27 seconds |
| Started | Sep 24 05:32:29 AM UTC 24 |
| Finished | Sep 24 05:35:08 AM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593183847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.593183847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/44.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.2533529343 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 99088041968 ps |
| CPU time | 60.19 seconds |
| Started | Sep 24 05:36:09 AM UTC 24 |
| Finished | Sep 24 05:37:11 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533529343 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2533529343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/50.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.1909607230 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 60545678710 ps |
| CPU time | 165.29 seconds |
| Started | Sep 24 05:36:44 AM UTC 24 |
| Finished | Sep 24 05:39:32 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909607230 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1909607230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/57.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.3445682226 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 261566466629 ps |
| CPU time | 536.86 seconds |
| Started | Sep 24 05:37:44 AM UTC 24 |
| Finished | Sep 24 05:46:48 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445682226 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3445682226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/67.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.773322013 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 150691193732 ps |
| CPU time | 864.92 seconds |
| Started | Sep 24 05:41:10 AM UTC 24 |
| Finished | Sep 24 05:55:46 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773322013 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.773322013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/84.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.2483476473 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 36739892408 ps |
| CPU time | 120.47 seconds |
| Started | Sep 24 05:41:41 AM UTC 24 |
| Finished | Sep 24 05:43:44 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483476473 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2483476473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/87.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2682516856 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 110340671 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 05:57:28 AM UTC 24 |
| Finished | Sep 24 05:57:30 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682516856 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.2682516856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2771425718 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 531805542 ps |
| CPU time | 5.71 seconds |
| Started | Sep 24 05:57:26 AM UTC 24 |
| Finished | Sep 24 05:57:34 AM UTC 24 |
| Peak memory | 200684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771425718 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.2771425718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1094110488 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 80848306 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 05:57:23 AM UTC 24 |
| Finished | Sep 24 05:57:25 AM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094110488 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.1094110488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.812826755 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 20075072 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 05:57:31 AM UTC 24 |
| Finished | Sep 24 05:57:33 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=812826755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr _mem_rw_with_rand_reset.812826755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.3618368125 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 16338794 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 05:57:24 AM UTC 24 |
| Finished | Sep 24 05:57:26 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618368125 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3618368125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.1629837838 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 38588180 ps |
| CPU time | 0.82 seconds |
| Started | Sep 24 05:57:20 AM UTC 24 |
| Finished | Sep 24 05:57:22 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629837838 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1629837838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.2406436139 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 58449508 ps |
| CPU time | 3.69 seconds |
| Started | Sep 24 05:57:12 AM UTC 24 |
| Finished | Sep 24 05:57:17 AM UTC 24 |
| Peak memory | 202792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406436139 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2406436139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.962445538 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 39446113 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 05:57:38 AM UTC 24 |
| Finished | Sep 24 05:57:40 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962445538 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.962445538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3268126493 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 713472915 ps |
| CPU time | 3.28 seconds |
| Started | Sep 24 05:57:37 AM UTC 24 |
| Finished | Sep 24 05:57:41 AM UTC 24 |
| Peak memory | 200680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268126493 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.3268126493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3653200156 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 21776815 ps |
| CPU time | 0.88 seconds |
| Started | Sep 24 05:57:36 AM UTC 24 |
| Finished | Sep 24 05:57:38 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653200156 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.3653200156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2385745510 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 38871098 ps |
| CPU time | 2.04 seconds |
| Started | Sep 24 05:57:39 AM UTC 24 |
| Finished | Sep 24 05:57:42 AM UTC 24 |
| Peak memory | 202792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2385745510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_cs r_mem_rw_with_rand_reset.2385745510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.687133038 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 29537447 ps |
| CPU time | 0.79 seconds |
| Started | Sep 24 05:57:35 AM UTC 24 |
| Finished | Sep 24 05:57:37 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687133038 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.687133038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1721895911 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 79002699 ps |
| CPU time | 0.94 seconds |
| Started | Sep 24 05:57:38 AM UTC 24 |
| Finished | Sep 24 05:57:40 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721895911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.1721895911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.1890088417 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 67859599 ps |
| CPU time | 2.87 seconds |
| Started | Sep 24 05:57:31 AM UTC 24 |
| Finished | Sep 24 05:57:35 AM UTC 24 |
| Peak memory | 200680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890088417 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1890088417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3633237026 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 61730664 ps |
| CPU time | 2.46 seconds |
| Started | Sep 24 05:58:11 AM UTC 24 |
| Finished | Sep 24 05:58:14 AM UTC 24 |
| Peak memory | 202788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3633237026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_c sr_mem_rw_with_rand_reset.3633237026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.2114640442 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 32455266 ps |
| CPU time | 0.82 seconds |
| Started | Sep 24 05:58:10 AM UTC 24 |
| Finished | Sep 24 05:58:12 AM UTC 24 |
| Peak memory | 199048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114640442 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2114640442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.2399777437 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 40723645 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 05:58:10 AM UTC 24 |
| Finished | Sep 24 05:58:12 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399777437 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2399777437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/10.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3103030249 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 23419299 ps |
| CPU time | 1.05 seconds |
| Started | Sep 24 05:58:10 AM UTC 24 |
| Finished | Sep 24 05:58:12 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103030249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.3103030249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.1123613859 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 33907875 ps |
| CPU time | 1.84 seconds |
| Started | Sep 24 05:58:08 AM UTC 24 |
| Finished | Sep 24 05:58:11 AM UTC 24 |
| Peak memory | 199096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123613859 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1123613859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2136140199 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 85293760 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 05:58:10 AM UTC 24 |
| Finished | Sep 24 05:58:12 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136140199 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.2136140199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1048981276 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 56115767 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 05:58:13 AM UTC 24 |
| Finished | Sep 24 05:58:15 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1048981276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_c sr_mem_rw_with_rand_reset.1048981276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.3069519014 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 15373554 ps |
| CPU time | 0.89 seconds |
| Started | Sep 24 05:58:12 AM UTC 24 |
| Finished | Sep 24 05:58:14 AM UTC 24 |
| Peak memory | 199048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069519014 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3069519014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.1796406062 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 38049007 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 05:58:12 AM UTC 24 |
| Finished | Sep 24 05:58:14 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796406062 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1796406062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/11.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.47420846 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 20049092 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 05:58:12 AM UTC 24 |
| Finished | Sep 24 05:58:14 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47420846 -assert nopostproc + UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.47420846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.2997981864 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 177263728 ps |
| CPU time | 4.19 seconds |
| Started | Sep 24 05:58:11 AM UTC 24 |
| Finished | Sep 24 05:58:16 AM UTC 24 |
| Peak memory | 200884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997981864 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2997981864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2120861830 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 270612774 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 05:58:11 AM UTC 24 |
| Finished | Sep 24 05:58:14 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120861830 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.2120861830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.127548582 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 107656023 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 05:58:16 AM UTC 24 |
| Finished | Sep 24 05:58:19 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=127548582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_cs r_mem_rw_with_rand_reset.127548582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.3070678299 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 18216045 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 05:58:15 AM UTC 24 |
| Finished | Sep 24 05:58:17 AM UTC 24 |
| Peak memory | 199048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070678299 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3070678299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.1021295202 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 13398121 ps |
| CPU time | 0.84 seconds |
| Started | Sep 24 05:58:15 AM UTC 24 |
| Finished | Sep 24 05:58:17 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021295202 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1021295202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/12.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4056867030 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 195851717 ps |
| CPU time | 0.98 seconds |
| Started | Sep 24 05:58:15 AM UTC 24 |
| Finished | Sep 24 05:58:17 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056867030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.4056867030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.3705832881 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 184460418 ps |
| CPU time | 4.35 seconds |
| Started | Sep 24 05:58:14 AM UTC 24 |
| Finished | Sep 24 05:58:19 AM UTC 24 |
| Peak memory | 202792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705832881 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3705832881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2813656913 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 150042643 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 05:58:15 AM UTC 24 |
| Finished | Sep 24 05:58:17 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813656913 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.2813656913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2124455160 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 117726127 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 05:58:19 AM UTC 24 |
| Finished | Sep 24 05:58:22 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2124455160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_c sr_mem_rw_with_rand_reset.2124455160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.1009789542 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 28789325 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 05:58:18 AM UTC 24 |
| Finished | Sep 24 05:58:20 AM UTC 24 |
| Peak memory | 199048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009789542 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1009789542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.1586714471 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 13503824 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 05:58:18 AM UTC 24 |
| Finished | Sep 24 05:58:20 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586714471 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1586714471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/13.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1913421720 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 46002085 ps |
| CPU time | 1.03 seconds |
| Started | Sep 24 05:58:18 AM UTC 24 |
| Finished | Sep 24 05:58:20 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913421720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.1913421720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.771962447 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 50515556 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 05:58:16 AM UTC 24 |
| Finished | Sep 24 05:58:19 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771962447 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.771962447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1971398203 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 273724404 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 05:58:18 AM UTC 24 |
| Finished | Sep 24 05:58:20 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971398203 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.1971398203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.723834304 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 59645158 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 05:58:21 AM UTC 24 |
| Finished | Sep 24 05:58:23 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=723834304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_cs r_mem_rw_with_rand_reset.723834304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1157927179 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 22376155 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 05:58:21 AM UTC 24 |
| Finished | Sep 24 05:58:23 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157927179 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1157927179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.251653736 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 15475928 ps |
| CPU time | 0.81 seconds |
| Started | Sep 24 05:58:20 AM UTC 24 |
| Finished | Sep 24 05:58:22 AM UTC 24 |
| Peak memory | 198784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251653736 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.251653736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/14.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2426518180 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 37823539 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 05:58:21 AM UTC 24 |
| Finished | Sep 24 05:58:23 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426518180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.2426518180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.3033414767 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 80845768 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 05:58:19 AM UTC 24 |
| Finished | Sep 24 05:58:22 AM UTC 24 |
| Peak memory | 199096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033414767 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3033414767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.911422171 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 39432603 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 05:58:20 AM UTC 24 |
| Finished | Sep 24 05:58:23 AM UTC 24 |
| Peak memory | 198860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911422171 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.911422171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3410112411 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 21250419 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 05:58:23 AM UTC 24 |
| Finished | Sep 24 05:58:26 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3410112411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c sr_mem_rw_with_rand_reset.3410112411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.2547540296 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 22754655 ps |
| CPU time | 0.94 seconds |
| Started | Sep 24 05:58:23 AM UTC 24 |
| Finished | Sep 24 05:58:25 AM UTC 24 |
| Peak memory | 199048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547540296 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2547540296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.231693060 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 30785252 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 05:58:23 AM UTC 24 |
| Finished | Sep 24 05:58:25 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231693060 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.231693060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/15.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2123923780 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 14133565 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 05:58:23 AM UTC 24 |
| Finished | Sep 24 05:58:25 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123923780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.2123923780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.3097168521 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 112536827 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 05:58:21 AM UTC 24 |
| Finished | Sep 24 05:58:25 AM UTC 24 |
| Peak memory | 200588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097168521 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3097168521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3498038143 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 69349270 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 05:58:22 AM UTC 24 |
| Finished | Sep 24 05:58:25 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498038143 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.3498038143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2312989537 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 32414348 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 05:58:26 AM UTC 24 |
| Finished | Sep 24 05:58:29 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2312989537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_c sr_mem_rw_with_rand_reset.2312989537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.2940776657 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 26004552 ps |
| CPU time | 0.89 seconds |
| Started | Sep 24 05:58:25 AM UTC 24 |
| Finished | Sep 24 05:58:27 AM UTC 24 |
| Peak memory | 199048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940776657 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2940776657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.510292056 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 13316106 ps |
| CPU time | 0.84 seconds |
| Started | Sep 24 05:58:25 AM UTC 24 |
| Finished | Sep 24 05:58:26 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510292056 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.510292056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/16.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2293540435 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 61195035 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 05:58:26 AM UTC 24 |
| Finished | Sep 24 05:58:29 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293540435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.2293540435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.92178928 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 269378985 ps |
| CPU time | 2.17 seconds |
| Started | Sep 24 05:58:23 AM UTC 24 |
| Finished | Sep 24 05:58:27 AM UTC 24 |
| Peak memory | 200748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92178928 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.92178928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3026354039 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 309641674 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 05:58:23 AM UTC 24 |
| Finished | Sep 24 05:58:26 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026354039 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.3026354039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2577227353 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 49216647 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 05:58:28 AM UTC 24 |
| Finished | Sep 24 05:58:30 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2577227353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_c sr_mem_rw_with_rand_reset.2577227353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.3441563699 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 36769229 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 05:58:28 AM UTC 24 |
| Finished | Sep 24 05:58:30 AM UTC 24 |
| Peak memory | 199048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441563699 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3441563699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.3212716551 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 13764250 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 05:58:26 AM UTC 24 |
| Finished | Sep 24 05:58:28 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212716551 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3212716551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/17.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1690441712 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 56113260 ps |
| CPU time | 1.05 seconds |
| Started | Sep 24 05:58:28 AM UTC 24 |
| Finished | Sep 24 05:58:30 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690441712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.1690441712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.3307149369 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 170942103 ps |
| CPU time | 2.54 seconds |
| Started | Sep 24 05:58:26 AM UTC 24 |
| Finished | Sep 24 05:58:30 AM UTC 24 |
| Peak memory | 200744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307149369 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3307149369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3018572449 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 149654093 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 05:58:26 AM UTC 24 |
| Finished | Sep 24 05:58:29 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018572449 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.3018572449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1444224412 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 19197293 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 05:58:29 AM UTC 24 |
| Finished | Sep 24 05:58:32 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1444224412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_c sr_mem_rw_with_rand_reset.1444224412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.3696692646 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 40668019 ps |
| CPU time | 0.84 seconds |
| Started | Sep 24 05:58:29 AM UTC 24 |
| Finished | Sep 24 05:58:31 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696692646 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3696692646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.2112170026 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 197471144 ps |
| CPU time | 0.84 seconds |
| Started | Sep 24 05:58:29 AM UTC 24 |
| Finished | Sep 24 05:58:31 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112170026 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2112170026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/18.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3322551857 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 99240187 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 05:58:29 AM UTC 24 |
| Finished | Sep 24 05:58:31 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322551857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.3322551857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.1341074781 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 83919494 ps |
| CPU time | 2.34 seconds |
| Started | Sep 24 05:58:28 AM UTC 24 |
| Finished | Sep 24 05:58:31 AM UTC 24 |
| Peak memory | 200696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341074781 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1341074781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1551588512 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 175516970 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 05:58:28 AM UTC 24 |
| Finished | Sep 24 05:58:31 AM UTC 24 |
| Peak memory | 200692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551588512 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.1551588512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3084089242 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 156297662 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 05:58:32 AM UTC 24 |
| Finished | Sep 24 05:58:35 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3084089242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_c sr_mem_rw_with_rand_reset.3084089242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.1508715436 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 13386606 ps |
| CPU time | 0.84 seconds |
| Started | Sep 24 05:58:31 AM UTC 24 |
| Finished | Sep 24 05:58:33 AM UTC 24 |
| Peak memory | 199048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508715436 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1508715436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.4185202157 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 35291250 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 05:58:31 AM UTC 24 |
| Finished | Sep 24 05:58:33 AM UTC 24 |
| Peak memory | 198880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185202157 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4185202157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/19.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1269820936 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 54237488 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 05:58:32 AM UTC 24 |
| Finished | Sep 24 05:58:34 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269820936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.1269820936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.2915528215 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 207845227 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 05:58:31 AM UTC 24 |
| Finished | Sep 24 05:58:33 AM UTC 24 |
| Peak memory | 199096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915528215 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2915528215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2600640533 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 114221516 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 05:58:31 AM UTC 24 |
| Finished | Sep 24 05:58:34 AM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600640533 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.2600640533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2071185601 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 26088579 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 05:57:44 AM UTC 24 |
| Finished | Sep 24 05:57:46 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071185601 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.2071185601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.814031113 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 123259709 ps |
| CPU time | 3.35 seconds |
| Started | Sep 24 05:57:44 AM UTC 24 |
| Finished | Sep 24 05:57:48 AM UTC 24 |
| Peak memory | 200948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814031113 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.814031113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2372702128 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 59008204 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 05:57:43 AM UTC 24 |
| Finished | Sep 24 05:57:45 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372702128 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.2372702128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1546 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 21450251 ps |
| CPU time | 1.05 seconds |
| Started | Sep 24 05:57:45 AM UTC 24 |
| Finished | Sep 24 05:57:47 AM UTC 24 |
| Peak memory | 198356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_ rw_with_rand_reset.1546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.1886482030 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 24014355 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 05:57:43 AM UTC 24 |
| Finished | Sep 24 05:57:45 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886482030 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1886482030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.2714000010 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 56505985 ps |
| CPU time | 0.97 seconds |
| Started | Sep 24 05:57:43 AM UTC 24 |
| Finished | Sep 24 05:57:45 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714000010 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2714000010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.561047131 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 12348955 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 05:57:45 AM UTC 24 |
| Finished | Sep 24 05:57:47 AM UTC 24 |
| Peak memory | 198600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561047131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.561047131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.1404247866 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 36202314 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 05:57:41 AM UTC 24 |
| Finished | Sep 24 05:57:44 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404247866 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1404247866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3497254957 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 343381969 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 05:57:41 AM UTC 24 |
| Finished | Sep 24 05:57:44 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497254957 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.3497254957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.1163495091 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 22249171 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 05:58:32 AM UTC 24 |
| Finished | Sep 24 05:58:34 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163495091 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1163495091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/20.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.403415799 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 81815815 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 05:58:33 AM UTC 24 |
| Finished | Sep 24 05:58:34 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403415799 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.403415799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/21.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.1506204901 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 45525545 ps |
| CPU time | 0.81 seconds |
| Started | Sep 24 05:58:33 AM UTC 24 |
| Finished | Sep 24 05:58:34 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506204901 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1506204901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/22.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.660015445 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 28162467 ps |
| CPU time | 0.82 seconds |
| Started | Sep 24 05:58:33 AM UTC 24 |
| Finished | Sep 24 05:58:34 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660015445 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.660015445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/23.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.149554994 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 21468854 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 05:58:34 AM UTC 24 |
| Finished | Sep 24 05:58:36 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149554994 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.149554994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/24.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1602183770 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 27385940 ps |
| CPU time | 0.81 seconds |
| Started | Sep 24 05:58:34 AM UTC 24 |
| Finished | Sep 24 05:58:36 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602183770 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1602183770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/25.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.559349551 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 15085984 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 05:58:34 AM UTC 24 |
| Finished | Sep 24 05:58:36 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559349551 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.559349551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/26.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.2161530945 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 27173717 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 05:58:35 AM UTC 24 |
| Finished | Sep 24 05:58:37 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161530945 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2161530945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/27.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.3653076145 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 70850292 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 05:58:35 AM UTC 24 |
| Finished | Sep 24 05:58:37 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653076145 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3653076145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/28.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.4189409444 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 12758671 ps |
| CPU time | 0.88 seconds |
| Started | Sep 24 05:58:36 AM UTC 24 |
| Finished | Sep 24 05:58:37 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189409444 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.4189409444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/29.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.174728699 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 35070116 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 05:57:50 AM UTC 24 |
| Finished | Sep 24 05:57:52 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174728699 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.174728699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2643275475 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 428993621 ps |
| CPU time | 4.66 seconds |
| Started | Sep 24 05:57:48 AM UTC 24 |
| Finished | Sep 24 05:57:54 AM UTC 24 |
| Peak memory | 200740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643275475 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.2643275475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2068587683 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 15855416 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 05:57:47 AM UTC 24 |
| Finished | Sep 24 05:57:49 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068587683 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.2068587683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2936562440 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 33293383 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 05:57:50 AM UTC 24 |
| Finished | Sep 24 05:57:52 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2936562440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_cs r_mem_rw_with_rand_reset.2936562440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.3821910998 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 17754061 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 05:57:48 AM UTC 24 |
| Finished | Sep 24 05:57:50 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821910998 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3821910998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.4218246669 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 44043508 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 05:57:46 AM UTC 24 |
| Finished | Sep 24 05:57:48 AM UTC 24 |
| Peak memory | 198844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218246669 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.4218246669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.556338644 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 63650128 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 05:57:50 AM UTC 24 |
| Finished | Sep 24 05:57:52 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556338644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.556338644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.158532060 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 149978207 ps |
| CPU time | 2.81 seconds |
| Started | Sep 24 05:57:45 AM UTC 24 |
| Finished | Sep 24 05:57:49 AM UTC 24 |
| Peak memory | 200676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158532060 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.158532060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3034391632 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 216441514 ps |
| CPU time | 2.03 seconds |
| Started | Sep 24 05:57:45 AM UTC 24 |
| Finished | Sep 24 05:57:48 AM UTC 24 |
| Peak memory | 200820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034391632 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.3034391632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.2879413030 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 31412628 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 05:58:36 AM UTC 24 |
| Finished | Sep 24 05:58:37 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879413030 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2879413030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/30.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.2078746176 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 14083027 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 05:58:36 AM UTC 24 |
| Finished | Sep 24 05:58:38 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078746176 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2078746176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/31.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.3290422590 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 16753020 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 05:58:36 AM UTC 24 |
| Finished | Sep 24 05:58:38 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290422590 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3290422590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/32.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.194648347 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 34208979 ps |
| CPU time | 0.88 seconds |
| Started | Sep 24 05:58:37 AM UTC 24 |
| Finished | Sep 24 05:58:39 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194648347 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.194648347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/33.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.4114161700 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 10848328 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 05:58:37 AM UTC 24 |
| Finished | Sep 24 05:58:39 AM UTC 24 |
| Peak memory | 198964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114161700 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4114161700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/34.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.1921988863 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 16191051 ps |
| CPU time | 0.89 seconds |
| Started | Sep 24 05:58:37 AM UTC 24 |
| Finished | Sep 24 05:58:39 AM UTC 24 |
| Peak memory | 198964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921988863 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1921988863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/35.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.2901659717 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 44094645 ps |
| CPU time | 0.82 seconds |
| Started | Sep 24 05:58:37 AM UTC 24 |
| Finished | Sep 24 05:58:39 AM UTC 24 |
| Peak memory | 198888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901659717 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2901659717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/36.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.375266844 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 44369862 ps |
| CPU time | 0.89 seconds |
| Started | Sep 24 05:58:37 AM UTC 24 |
| Finished | Sep 24 05:58:39 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375266844 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.375266844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/37.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.2593193058 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 13953923 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 05:58:39 AM UTC 24 |
| Finished | Sep 24 05:58:41 AM UTC 24 |
| Peak memory | 198960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593193058 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2593193058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/38.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.197516301 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 18243282 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 05:58:39 AM UTC 24 |
| Finished | Sep 24 05:58:41 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197516301 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.197516301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/39.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.435766534 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 68062375 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 05:57:54 AM UTC 24 |
| Finished | Sep 24 05:57:56 AM UTC 24 |
| Peak memory | 198868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435766534 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.435766534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2114493576 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 527771972 ps |
| CPU time | 2.35 seconds |
| Started | Sep 24 05:57:53 AM UTC 24 |
| Finished | Sep 24 05:57:56 AM UTC 24 |
| Peak memory | 200748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114493576 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.2114493576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1257708999 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 21718543 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 05:57:53 AM UTC 24 |
| Finished | Sep 24 05:57:55 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257708999 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.1257708999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1531774136 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 20501131 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 05:57:56 AM UTC 24 |
| Finished | Sep 24 05:57:58 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1531774136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_cs r_mem_rw_with_rand_reset.1531774136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.3159367756 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 44366582 ps |
| CPU time | 0.94 seconds |
| Started | Sep 24 05:57:53 AM UTC 24 |
| Finished | Sep 24 05:57:55 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159367756 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3159367756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.477438033 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 16280890 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 05:57:53 AM UTC 24 |
| Finished | Sep 24 05:57:55 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477438033 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.477438033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1150081685 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 144067562 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 05:57:54 AM UTC 24 |
| Finished | Sep 24 05:57:56 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150081685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.1150081685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.2741445711 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 28793009 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 05:57:50 AM UTC 24 |
| Finished | Sep 24 05:57:53 AM UTC 24 |
| Peak memory | 202932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741445711 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2741445711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.224105261 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 82549908 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 05:57:51 AM UTC 24 |
| Finished | Sep 24 05:57:53 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224105261 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.224105261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2412381681 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 116918278 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 05:58:39 AM UTC 24 |
| Finished | Sep 24 05:58:41 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412381681 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2412381681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/40.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.3963156223 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 11393169 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 05:58:39 AM UTC 24 |
| Finished | Sep 24 05:58:41 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963156223 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3963156223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/41.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.3955655837 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 17594109 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 05:58:39 AM UTC 24 |
| Finished | Sep 24 05:58:41 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955655837 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3955655837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/42.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.4074129590 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 24568354 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 05:58:39 AM UTC 24 |
| Finished | Sep 24 05:58:41 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074129590 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4074129590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/43.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.2078838930 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 16475711 ps |
| CPU time | 0.94 seconds |
| Started | Sep 24 05:58:40 AM UTC 24 |
| Finished | Sep 24 05:58:42 AM UTC 24 |
| Peak memory | 198692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078838930 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2078838930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/44.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.3121015267 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 35459342 ps |
| CPU time | 0.84 seconds |
| Started | Sep 24 05:58:41 AM UTC 24 |
| Finished | Sep 24 05:58:42 AM UTC 24 |
| Peak memory | 198720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121015267 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3121015267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/45.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.3422515852 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 30071636 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 05:58:41 AM UTC 24 |
| Finished | Sep 24 05:58:42 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422515852 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3422515852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/46.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.3836789644 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 14996035 ps |
| CPU time | 0.84 seconds |
| Started | Sep 24 05:58:41 AM UTC 24 |
| Finished | Sep 24 05:58:42 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836789644 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3836789644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/47.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.4120189911 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 42216625 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 05:58:41 AM UTC 24 |
| Finished | Sep 24 05:58:42 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120189911 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.4120189911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/48.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.4071116356 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 16185026 ps |
| CPU time | 0.82 seconds |
| Started | Sep 24 05:58:42 AM UTC 24 |
| Finished | Sep 24 05:58:44 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071116356 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.4071116356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/49.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.921751363 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 91574350 ps |
| CPU time | 1.78 seconds |
| Started | Sep 24 05:57:58 AM UTC 24 |
| Finished | Sep 24 05:58:01 AM UTC 24 |
| Peak memory | 198844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=921751363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr _mem_rw_with_rand_reset.921751363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.1164679193 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 12793835 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 05:57:57 AM UTC 24 |
| Finished | Sep 24 05:57:59 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164679193 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1164679193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.1341501326 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 38445720 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 05:57:56 AM UTC 24 |
| Finished | Sep 24 05:57:58 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341501326 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1341501326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/5.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2811798161 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 69354178 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 05:57:58 AM UTC 24 |
| Finished | Sep 24 05:58:00 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811798161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.2811798161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.295977432 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 68443774 ps |
| CPU time | 2.1 seconds |
| Started | Sep 24 05:57:56 AM UTC 24 |
| Finished | Sep 24 05:57:59 AM UTC 24 |
| Peak memory | 200876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295977432 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.295977432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.974591426 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 73563937 ps |
| CPU time | 1.67 seconds |
| Started | Sep 24 05:57:56 AM UTC 24 |
| Finished | Sep 24 05:57:58 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974591426 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.974591426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.988180447 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 31221957 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 05:58:00 AM UTC 24 |
| Finished | Sep 24 05:58:03 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=988180447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr _mem_rw_with_rand_reset.988180447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.3624898125 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 34017367 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 05:57:59 AM UTC 24 |
| Finished | Sep 24 05:58:01 AM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624898125 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3624898125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.1668295383 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 51354061 ps |
| CPU time | 0.82 seconds |
| Started | Sep 24 05:57:59 AM UTC 24 |
| Finished | Sep 24 05:58:01 AM UTC 24 |
| Peak memory | 198668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668295383 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1668295383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/6.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2716244333 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 52757164 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 05:57:59 AM UTC 24 |
| Finished | Sep 24 05:58:01 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716244333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.2716244333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.521003417 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 61655256 ps |
| CPU time | 4.47 seconds |
| Started | Sep 24 05:57:58 AM UTC 24 |
| Finished | Sep 24 05:58:04 AM UTC 24 |
| Peak memory | 200876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521003417 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.521003417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2631899190 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 100105358 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 05:57:59 AM UTC 24 |
| Finished | Sep 24 05:58:02 AM UTC 24 |
| Peak memory | 198472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631899190 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.2631899190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3661616092 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 34500962 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 05:58:03 AM UTC 24 |
| Finished | Sep 24 05:58:05 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3661616092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_cs r_mem_rw_with_rand_reset.3661616092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.2374740120 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 13662229 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 05:58:02 AM UTC 24 |
| Finished | Sep 24 05:58:04 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374740120 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2374740120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.1908889395 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 16463747 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 05:58:02 AM UTC 24 |
| Finished | Sep 24 05:58:04 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908889395 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1908889395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/7.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1558469101 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 70332048 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 05:58:02 AM UTC 24 |
| Finished | Sep 24 05:58:04 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558469101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.1558469101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.2853623369 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 98327366 ps |
| CPU time | 1.78 seconds |
| Started | Sep 24 05:58:02 AM UTC 24 |
| Finished | Sep 24 05:58:05 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853623369 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2853623369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3456062629 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 317451725 ps |
| CPU time | 1.83 seconds |
| Started | Sep 24 05:58:02 AM UTC 24 |
| Finished | Sep 24 05:58:05 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456062629 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.3456062629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1811430335 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 25905423 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 05:58:06 AM UTC 24 |
| Finished | Sep 24 05:58:08 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1811430335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs r_mem_rw_with_rand_reset.1811430335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.1856919662 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 129975897 ps |
| CPU time | 0.88 seconds |
| Started | Sep 24 05:58:04 AM UTC 24 |
| Finished | Sep 24 05:58:06 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856919662 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1856919662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.1345619149 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 11748229 ps |
| CPU time | 0.8 seconds |
| Started | Sep 24 05:58:04 AM UTC 24 |
| Finished | Sep 24 05:58:06 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345619149 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1345619149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/8.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2211054057 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 48579518 ps |
| CPU time | 1.05 seconds |
| Started | Sep 24 05:58:06 AM UTC 24 |
| Finished | Sep 24 05:58:08 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211054057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.2211054057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.1052041403 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 694798744 ps |
| CPU time | 4.1 seconds |
| Started | Sep 24 05:58:04 AM UTC 24 |
| Finished | Sep 24 05:58:09 AM UTC 24 |
| Peak memory | 200620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052041403 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1052041403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1432901138 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 392697880 ps |
| CPU time | 1.98 seconds |
| Started | Sep 24 05:58:04 AM UTC 24 |
| Finished | Sep 24 05:58:07 AM UTC 24 |
| Peak memory | 199032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432901138 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.1432901138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.703487044 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 24390042 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 05:58:08 AM UTC 24 |
| Finished | Sep 24 05:58:10 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=703487044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr _mem_rw_with_rand_reset.703487044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.2114808235 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 176826972 ps |
| CPU time | 0.89 seconds |
| Started | Sep 24 05:58:07 AM UTC 24 |
| Finished | Sep 24 05:58:09 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114808235 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2114808235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.3265835202 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 68556459 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 05:58:07 AM UTC 24 |
| Finished | Sep 24 05:58:09 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265835202 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3265835202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/9.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.499728777 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 60269160 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 05:58:08 AM UTC 24 |
| Finished | Sep 24 05:58:10 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499728777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.499728777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.2373677485 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 24600478 ps |
| CPU time | 1.86 seconds |
| Started | Sep 24 05:58:06 AM UTC 24 |
| Finished | Sep 24 05:58:09 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373677485 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2373677485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.306194576 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 387164265 ps |
| CPU time | 1.62 seconds |
| Started | Sep 24 05:58:06 AM UTC 24 |
| Finished | Sep 24 05:58:08 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306194576 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.306194576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.195472991 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 959960171797 ps |
| CPU time | 356.87 seconds |
| Started | Sep 24 05:12:38 AM UTC 24 |
| Finished | Sep 24 05:18:40 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195472991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.195472991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.563190383 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 331794321 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 05:12:41 AM UTC 24 |
| Finished | Sep 24 05:12:43 AM UTC 24 |
| Peak memory | 200348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563190383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.563190383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/0.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.590687868 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 145673993238 ps |
| CPU time | 248.29 seconds |
| Started | Sep 24 05:12:49 AM UTC 24 |
| Finished | Sep 24 05:17:01 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590687868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.590687868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.134480693 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 149971633791 ps |
| CPU time | 926.42 seconds |
| Started | Sep 24 05:12:53 AM UTC 24 |
| Finished | Sep 24 05:28:31 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134480693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.134480693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.524749581 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 60161131 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 05:12:58 AM UTC 24 |
| Finished | Sep 24 05:13:01 AM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524749581 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.524749581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.3316507237 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 124460875796 ps |
| CPU time | 285.33 seconds |
| Started | Sep 24 05:15:21 AM UTC 24 |
| Finished | Sep 24 05:20:10 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316507237 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.3316507237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.3907051388 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 74640755988 ps |
| CPU time | 63.76 seconds |
| Started | Sep 24 05:15:16 AM UTC 24 |
| Finished | Sep 24 05:16:22 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907051388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3907051388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/10.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.2674686827 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 99789259571 ps |
| CPU time | 140.36 seconds |
| Started | Sep 24 05:15:13 AM UTC 24 |
| Finished | Sep 24 05:17:36 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674686827 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2674686827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/10.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.2085299527 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 120627917319 ps |
| CPU time | 92.78 seconds |
| Started | Sep 24 05:15:28 AM UTC 24 |
| Finished | Sep 24 05:17:03 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085299527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2085299527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/10.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.1491590611 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 111248974 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 05:15:38 AM UTC 24 |
| Finished | Sep 24 05:15:39 AM UTC 24 |
| Peak memory | 199488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491590611 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.1491590611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/10.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.1125904481 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 112034741328 ps |
| CPU time | 258.04 seconds |
| Started | Sep 24 05:43:06 AM UTC 24 |
| Finished | Sep 24 05:47:28 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125904481 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1125904481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/100.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.752506447 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 20388780849 ps |
| CPU time | 150.62 seconds |
| Started | Sep 24 05:43:44 AM UTC 24 |
| Finished | Sep 24 05:46:17 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752506447 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.752506447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/103.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.2536482287 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 39684358880 ps |
| CPU time | 324.48 seconds |
| Started | Sep 24 05:43:45 AM UTC 24 |
| Finished | Sep 24 05:49:14 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536482287 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2536482287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/104.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.4277194701 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 164919633429 ps |
| CPU time | 147.76 seconds |
| Started | Sep 24 05:44:05 AM UTC 24 |
| Finished | Sep 24 05:46:36 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277194701 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.4277194701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/105.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.1194946111 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 405153127742 ps |
| CPU time | 2407.61 seconds |
| Started | Sep 24 05:44:07 AM UTC 24 |
| Finished | Sep 24 06:24:44 AM UTC 24 |
| Peak memory | 202768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194946111 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1194946111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/106.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.2495069961 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 291567162806 ps |
| CPU time | 229.31 seconds |
| Started | Sep 24 05:44:08 AM UTC 24 |
| Finished | Sep 24 05:48:01 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495069961 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2495069961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/107.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.2429278988 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 138520065739 ps |
| CPU time | 217.05 seconds |
| Started | Sep 24 05:44:33 AM UTC 24 |
| Finished | Sep 24 05:48:13 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429278988 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2429278988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/109.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.1178257113 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 13476951981 ps |
| CPU time | 36.94 seconds |
| Started | Sep 24 05:15:43 AM UTC 24 |
| Finished | Sep 24 05:16:21 AM UTC 24 |
| Peak memory | 201020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178257113 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.1178257113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.2487188482 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 112928137933 ps |
| CPU time | 162.88 seconds |
| Started | Sep 24 05:15:40 AM UTC 24 |
| Finished | Sep 24 05:18:25 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487188482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2487188482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/11.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.4076672847 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 446574656652 ps |
| CPU time | 316.91 seconds |
| Started | Sep 24 05:15:40 AM UTC 24 |
| Finished | Sep 24 05:21:01 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076672847 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.4076672847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/11.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.1954923735 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 33395407756 ps |
| CPU time | 36.17 seconds |
| Started | Sep 24 05:15:53 AM UTC 24 |
| Finished | Sep 24 05:16:31 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954923735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1954923735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/11.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.3736569558 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2143948631341 ps |
| CPU time | 2354.94 seconds |
| Started | Sep 24 05:16:02 AM UTC 24 |
| Finished | Sep 24 05:55:43 AM UTC 24 |
| Peak memory | 202960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736569558 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.3736569558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/11.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all_with_rand_reset.580166892 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7835445578 ps |
| CPU time | 36.62 seconds |
| Started | Sep 24 05:15:59 AM UTC 24 |
| Finished | Sep 24 05:16:38 AM UTC 24 |
| Peak memory | 205368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=580166892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.580166892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/11.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.1929104973 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 90096793826 ps |
| CPU time | 86.39 seconds |
| Started | Sep 24 05:44:49 AM UTC 24 |
| Finished | Sep 24 05:46:17 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929104973 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1929104973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/110.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.614506639 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 483194805209 ps |
| CPU time | 1184.34 seconds |
| Started | Sep 24 05:45:03 AM UTC 24 |
| Finished | Sep 24 06:05:01 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614506639 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.614506639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/113.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.2581595877 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 73916113620 ps |
| CPU time | 72.69 seconds |
| Started | Sep 24 05:45:13 AM UTC 24 |
| Finished | Sep 24 05:46:28 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581595877 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2581595877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/115.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.3991385580 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 42504238972 ps |
| CPU time | 191.77 seconds |
| Started | Sep 24 05:46:10 AM UTC 24 |
| Finished | Sep 24 05:49:25 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991385580 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3991385580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/117.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.3821669036 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 93596425215 ps |
| CPU time | 83.09 seconds |
| Started | Sep 24 05:46:18 AM UTC 24 |
| Finished | Sep 24 05:47:43 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821669036 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3821669036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/118.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.3419855744 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 65862666841 ps |
| CPU time | 806.99 seconds |
| Started | Sep 24 05:46:18 AM UTC 24 |
| Finished | Sep 24 05:59:55 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419855744 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3419855744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/119.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.2755749952 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 147096210566 ps |
| CPU time | 121.64 seconds |
| Started | Sep 24 05:16:12 AM UTC 24 |
| Finished | Sep 24 05:18:16 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755749952 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.2755749952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.123224476 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 174082392369 ps |
| CPU time | 241.2 seconds |
| Started | Sep 24 05:16:04 AM UTC 24 |
| Finished | Sep 24 05:20:09 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123224476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.123224476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/12.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.2405322684 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 183767785580 ps |
| CPU time | 512.03 seconds |
| Started | Sep 24 05:16:02 AM UTC 24 |
| Finished | Sep 24 05:24:40 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405322684 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2405322684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/12.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.3877375299 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 222664817 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 05:16:16 AM UTC 24 |
| Finished | Sep 24 05:16:18 AM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877375299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3877375299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/12.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all_with_rand_reset.2769927459 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2474056376 ps |
| CPU time | 25.47 seconds |
| Started | Sep 24 05:16:19 AM UTC 24 |
| Finished | Sep 24 05:16:46 AM UTC 24 |
| Peak memory | 203240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2769927459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.rv_timer_stress_all_with_rand_reset.2769927459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/12.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.544446743 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 243720770870 ps |
| CPU time | 164.09 seconds |
| Started | Sep 24 05:46:24 AM UTC 24 |
| Finished | Sep 24 05:49:11 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544446743 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.544446743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/120.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.3498794644 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 337117698664 ps |
| CPU time | 443.47 seconds |
| Started | Sep 24 05:46:28 AM UTC 24 |
| Finished | Sep 24 05:53:58 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498794644 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3498794644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/121.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.1267578150 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 202481345363 ps |
| CPU time | 627.25 seconds |
| Started | Sep 24 05:46:36 AM UTC 24 |
| Finished | Sep 24 05:57:11 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267578150 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1267578150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/123.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.3197076887 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 117542050689 ps |
| CPU time | 100.9 seconds |
| Started | Sep 24 05:47:01 AM UTC 24 |
| Finished | Sep 24 05:48:44 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197076887 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3197076887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/125.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.1712473985 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 27501600458 ps |
| CPU time | 11.86 seconds |
| Started | Sep 24 05:47:17 AM UTC 24 |
| Finished | Sep 24 05:47:31 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712473985 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1712473985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/126.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.524120153 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 57023491088 ps |
| CPU time | 26.06 seconds |
| Started | Sep 24 05:47:21 AM UTC 24 |
| Finished | Sep 24 05:47:48 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524120153 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.524120153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/127.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.3789744580 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 67935190996 ps |
| CPU time | 182.4 seconds |
| Started | Sep 24 05:47:29 AM UTC 24 |
| Finished | Sep 24 05:50:34 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789744580 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3789744580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/128.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.1508708958 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 281339690050 ps |
| CPU time | 1463.16 seconds |
| Started | Sep 24 05:47:32 AM UTC 24 |
| Finished | Sep 24 06:12:12 AM UTC 24 |
| Peak memory | 202688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508708958 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1508708958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/129.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.2092808310 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 10285136146 ps |
| CPU time | 19.29 seconds |
| Started | Sep 24 05:16:29 AM UTC 24 |
| Finished | Sep 24 05:16:50 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092808310 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.2092808310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.452998190 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 329895882035 ps |
| CPU time | 253.91 seconds |
| Started | Sep 24 05:16:27 AM UTC 24 |
| Finished | Sep 24 05:20:45 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452998190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.452998190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/13.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all_with_rand_reset.553631750 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9277890681 ps |
| CPU time | 41.47 seconds |
| Started | Sep 24 05:16:33 AM UTC 24 |
| Finished | Sep 24 05:17:16 AM UTC 24 |
| Peak memory | 205240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=553631750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.553631750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/13.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.2568236815 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 12593939260 ps |
| CPU time | 11.87 seconds |
| Started | Sep 24 05:47:43 AM UTC 24 |
| Finished | Sep 24 05:47:56 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568236815 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2568236815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/130.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.2877510510 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 701659597541 ps |
| CPU time | 253.74 seconds |
| Started | Sep 24 05:47:44 AM UTC 24 |
| Finished | Sep 24 05:52:02 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877510510 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2877510510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/131.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.1355914856 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 56047136216 ps |
| CPU time | 333.06 seconds |
| Started | Sep 24 05:47:54 AM UTC 24 |
| Finished | Sep 24 05:53:32 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355914856 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1355914856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/134.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.1686303235 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 55989230074 ps |
| CPU time | 191.42 seconds |
| Started | Sep 24 05:47:56 AM UTC 24 |
| Finished | Sep 24 05:51:11 AM UTC 24 |
| Peak memory | 201004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686303235 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1686303235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/135.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.3426008998 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 36673901844 ps |
| CPU time | 50.34 seconds |
| Started | Sep 24 05:48:02 AM UTC 24 |
| Finished | Sep 24 05:48:55 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426008998 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3426008998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/137.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.3027694695 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 163974764168 ps |
| CPU time | 123.4 seconds |
| Started | Sep 24 05:48:04 AM UTC 24 |
| Finished | Sep 24 05:50:10 AM UTC 24 |
| Peak memory | 200916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027694695 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3027694695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/139.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.2792270030 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 45098213400 ps |
| CPU time | 72.96 seconds |
| Started | Sep 24 05:16:40 AM UTC 24 |
| Finished | Sep 24 05:17:54 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792270030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2792270030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/14.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.365133330 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 41792239434 ps |
| CPU time | 215.16 seconds |
| Started | Sep 24 05:16:40 AM UTC 24 |
| Finished | Sep 24 05:20:18 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365133330 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.365133330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/14.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.1765260937 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 538445975121 ps |
| CPU time | 351.45 seconds |
| Started | Sep 24 05:16:44 AM UTC 24 |
| Finished | Sep 24 05:22:40 AM UTC 24 |
| Peak memory | 201092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765260937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1765260937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/14.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.1324588460 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 42563803157 ps |
| CPU time | 160.42 seconds |
| Started | Sep 24 05:48:15 AM UTC 24 |
| Finished | Sep 24 05:50:58 AM UTC 24 |
| Peak memory | 201204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324588460 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1324588460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/140.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.115197202 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 56317425313 ps |
| CPU time | 104.47 seconds |
| Started | Sep 24 05:48:36 AM UTC 24 |
| Finished | Sep 24 05:50:22 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115197202 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.115197202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/142.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.1999422868 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 136780737181 ps |
| CPU time | 211.04 seconds |
| Started | Sep 24 05:48:45 AM UTC 24 |
| Finished | Sep 24 05:52:19 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999422868 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1999422868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/143.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.2831703633 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 162116911654 ps |
| CPU time | 281.58 seconds |
| Started | Sep 24 05:48:56 AM UTC 24 |
| Finished | Sep 24 05:53:42 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831703633 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2831703633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/145.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.2494720167 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 562209840178 ps |
| CPU time | 653.14 seconds |
| Started | Sep 24 05:49:12 AM UTC 24 |
| Finished | Sep 24 06:00:14 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494720167 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2494720167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/146.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.1571577994 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 195139369870 ps |
| CPU time | 767.27 seconds |
| Started | Sep 24 05:49:15 AM UTC 24 |
| Finished | Sep 24 06:02:12 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571577994 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1571577994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/148.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.574133666 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 335675079349 ps |
| CPU time | 209.93 seconds |
| Started | Sep 24 05:49:25 AM UTC 24 |
| Finished | Sep 24 05:52:58 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574133666 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.574133666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/149.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.3605495181 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 199992694054 ps |
| CPU time | 107.1 seconds |
| Started | Sep 24 05:16:54 AM UTC 24 |
| Finished | Sep 24 05:18:43 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605495181 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.3605495181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.4067886089 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 120276658465 ps |
| CPU time | 235.55 seconds |
| Started | Sep 24 05:16:54 AM UTC 24 |
| Finished | Sep 24 05:20:53 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067886089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.4067886089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/15.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.53542477 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 115839662022 ps |
| CPU time | 109.15 seconds |
| Started | Sep 24 05:16:51 AM UTC 24 |
| Finished | Sep 24 05:18:42 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53542477 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.53542477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/15.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.1068296531 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 70302027424 ps |
| CPU time | 139.84 seconds |
| Started | Sep 24 05:16:56 AM UTC 24 |
| Finished | Sep 24 05:19:18 AM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068296531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1068296531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/15.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all_with_rand_reset.3243237650 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3887225552 ps |
| CPU time | 61.19 seconds |
| Started | Sep 24 05:16:56 AM UTC 24 |
| Finished | Sep 24 05:17:59 AM UTC 24 |
| Peak memory | 205424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3243237650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.rv_timer_stress_all_with_rand_reset.3243237650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/15.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.1375534817 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 372831091037 ps |
| CPU time | 798.94 seconds |
| Started | Sep 24 05:49:49 AM UTC 24 |
| Finished | Sep 24 06:03:18 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375534817 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1375534817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/150.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.14752049 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 198414316553 ps |
| CPU time | 136.36 seconds |
| Started | Sep 24 05:50:10 AM UTC 24 |
| Finished | Sep 24 05:52:29 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14752049 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.14752049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/151.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.4140270523 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 59018146109 ps |
| CPU time | 126.28 seconds |
| Started | Sep 24 05:50:23 AM UTC 24 |
| Finished | Sep 24 05:52:31 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140270523 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.4140270523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/153.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.448571963 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 85825197815 ps |
| CPU time | 166.81 seconds |
| Started | Sep 24 05:50:23 AM UTC 24 |
| Finished | Sep 24 05:53:12 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448571963 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.448571963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/154.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.3605111020 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 8860859994 ps |
| CPU time | 6.76 seconds |
| Started | Sep 24 05:50:35 AM UTC 24 |
| Finished | Sep 24 05:50:43 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605111020 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3605111020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/155.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.3173299465 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 760539380775 ps |
| CPU time | 670.76 seconds |
| Started | Sep 24 05:50:36 AM UTC 24 |
| Finished | Sep 24 06:01:55 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173299465 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3173299465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/156.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.2532502234 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 81396927759 ps |
| CPU time | 1004.23 seconds |
| Started | Sep 24 05:50:50 AM UTC 24 |
| Finished | Sep 24 06:07:46 AM UTC 24 |
| Peak memory | 202764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532502234 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2532502234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/158.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.3498199081 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 31553531828 ps |
| CPU time | 70.28 seconds |
| Started | Sep 24 05:50:50 AM UTC 24 |
| Finished | Sep 24 05:52:02 AM UTC 24 |
| Peak memory | 201268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498199081 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3498199081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/159.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.587407992 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 13327525820 ps |
| CPU time | 25.45 seconds |
| Started | Sep 24 05:17:02 AM UTC 24 |
| Finished | Sep 24 05:17:29 AM UTC 24 |
| Peak memory | 200984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587407992 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.587407992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.2722115492 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 49322219639 ps |
| CPU time | 93.75 seconds |
| Started | Sep 24 05:16:58 AM UTC 24 |
| Finished | Sep 24 05:18:34 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722115492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2722115492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/16.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.1951988827 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 5751578113 ps |
| CPU time | 5.67 seconds |
| Started | Sep 24 05:16:57 AM UTC 24 |
| Finished | Sep 24 05:17:04 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951988827 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1951988827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/16.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.4120080762 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 103368537787 ps |
| CPU time | 98.93 seconds |
| Started | Sep 24 05:17:03 AM UTC 24 |
| Finished | Sep 24 05:18:44 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120080762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.4120080762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/16.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.439005544 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 401375406157 ps |
| CPU time | 678.65 seconds |
| Started | Sep 24 05:17:10 AM UTC 24 |
| Finished | Sep 24 05:28:36 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439005544 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.439005544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/16.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.4134397446 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 45177156668 ps |
| CPU time | 209.24 seconds |
| Started | Sep 24 05:50:52 AM UTC 24 |
| Finished | Sep 24 05:54:25 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134397446 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.4134397446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/160.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.3899281399 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 46371955137 ps |
| CPU time | 107.68 seconds |
| Started | Sep 24 05:50:59 AM UTC 24 |
| Finished | Sep 24 05:52:49 AM UTC 24 |
| Peak memory | 201184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899281399 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3899281399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/161.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.588243848 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 529900706493 ps |
| CPU time | 424.81 seconds |
| Started | Sep 24 05:51:13 AM UTC 24 |
| Finished | Sep 24 05:58:24 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588243848 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.588243848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/163.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.4050229465 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 132732221045 ps |
| CPU time | 117.18 seconds |
| Started | Sep 24 05:52:03 AM UTC 24 |
| Finished | Sep 24 05:54:02 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050229465 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.4050229465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/164.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.3173153239 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 111382195889 ps |
| CPU time | 799.31 seconds |
| Started | Sep 24 05:52:03 AM UTC 24 |
| Finished | Sep 24 06:05:32 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173153239 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3173153239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/165.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.3013125289 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 275060220442 ps |
| CPU time | 400.24 seconds |
| Started | Sep 24 05:52:03 AM UTC 24 |
| Finished | Sep 24 05:58:49 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013125289 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3013125289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/166.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.3428641161 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 938988960092 ps |
| CPU time | 406.44 seconds |
| Started | Sep 24 05:52:26 AM UTC 24 |
| Finished | Sep 24 05:59:18 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428641161 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3428641161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/168.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.807429074 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 776311005342 ps |
| CPU time | 403.21 seconds |
| Started | Sep 24 05:17:16 AM UTC 24 |
| Finished | Sep 24 05:24:04 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807429074 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.807429074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.156279320 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 168943471551 ps |
| CPU time | 165.92 seconds |
| Started | Sep 24 05:17:12 AM UTC 24 |
| Finished | Sep 24 05:20:00 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156279320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.156279320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/17.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.1109015676 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 540424870846 ps |
| CPU time | 301.63 seconds |
| Started | Sep 24 05:17:29 AM UTC 24 |
| Finished | Sep 24 05:22:35 AM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109015676 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.1109015676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/17.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.117078755 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 136280648488 ps |
| CPU time | 290.21 seconds |
| Started | Sep 24 05:52:32 AM UTC 24 |
| Finished | Sep 24 05:57:26 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117078755 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.117078755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/170.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.350550973 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 191012354140 ps |
| CPU time | 340.05 seconds |
| Started | Sep 24 05:52:50 AM UTC 24 |
| Finished | Sep 24 05:58:35 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350550973 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.350550973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/171.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.2153721847 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 15803178824 ps |
| CPU time | 29.67 seconds |
| Started | Sep 24 05:53:20 AM UTC 24 |
| Finished | Sep 24 05:53:52 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153721847 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2153721847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/174.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.2513294722 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 344785424541 ps |
| CPU time | 250.71 seconds |
| Started | Sep 24 05:53:27 AM UTC 24 |
| Finished | Sep 24 05:57:41 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513294722 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2513294722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/175.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.3067359812 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 39008890943 ps |
| CPU time | 24.94 seconds |
| Started | Sep 24 05:53:33 AM UTC 24 |
| Finished | Sep 24 05:53:59 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067359812 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3067359812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/177.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.1611242247 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 55489466383 ps |
| CPU time | 113.53 seconds |
| Started | Sep 24 05:53:43 AM UTC 24 |
| Finished | Sep 24 05:55:38 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611242247 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1611242247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/178.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.2210341378 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 91144368489 ps |
| CPU time | 765.19 seconds |
| Started | Sep 24 05:53:53 AM UTC 24 |
| Finished | Sep 24 06:06:48 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210341378 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2210341378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/179.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.4055846593 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 77552166440 ps |
| CPU time | 59.96 seconds |
| Started | Sep 24 05:17:31 AM UTC 24 |
| Finished | Sep 24 05:18:33 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055846593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.4055846593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/18.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.663513219 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 19088704 ps |
| CPU time | 0.74 seconds |
| Started | Sep 24 05:17:37 AM UTC 24 |
| Finished | Sep 24 05:17:39 AM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663513219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.663513219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/18.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.1685447320 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 215449735555 ps |
| CPU time | 451.58 seconds |
| Started | Sep 24 05:17:53 AM UTC 24 |
| Finished | Sep 24 05:25:31 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685447320 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.1685447320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/18.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.3679686684 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 84019149514 ps |
| CPU time | 171.96 seconds |
| Started | Sep 24 05:53:58 AM UTC 24 |
| Finished | Sep 24 05:56:53 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679686684 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3679686684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/180.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.979360890 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 114178444549 ps |
| CPU time | 204.17 seconds |
| Started | Sep 24 05:54:25 AM UTC 24 |
| Finished | Sep 24 05:57:52 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979360890 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.979360890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/185.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.348644061 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 330709756521 ps |
| CPU time | 375.78 seconds |
| Started | Sep 24 05:55:14 AM UTC 24 |
| Finished | Sep 24 06:01:35 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348644061 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.348644061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/187.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.1661090150 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 161259813475 ps |
| CPU time | 1403.34 seconds |
| Started | Sep 24 05:55:32 AM UTC 24 |
| Finished | Sep 24 06:19:12 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661090150 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1661090150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/189.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.3170478357 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 426768658452 ps |
| CPU time | 124.03 seconds |
| Started | Sep 24 05:18:00 AM UTC 24 |
| Finished | Sep 24 05:20:06 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170478357 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.3170478357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.4156717383 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 525847510827 ps |
| CPU time | 381.72 seconds |
| Started | Sep 24 05:17:59 AM UTC 24 |
| Finished | Sep 24 05:24:25 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156717383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.4156717383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/19.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.3087883902 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 90887271983 ps |
| CPU time | 102.95 seconds |
| Started | Sep 24 05:17:55 AM UTC 24 |
| Finished | Sep 24 05:19:40 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087883902 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3087883902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/19.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.71069255 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 82806318413 ps |
| CPU time | 149.9 seconds |
| Started | Sep 24 05:18:08 AM UTC 24 |
| Finished | Sep 24 05:20:41 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71069255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.71069255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/19.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.3697222720 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 122374764899 ps |
| CPU time | 205.21 seconds |
| Started | Sep 24 05:18:16 AM UTC 24 |
| Finished | Sep 24 05:21:44 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697222720 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.3697222720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/19.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.1646019774 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 171392607408 ps |
| CPU time | 1368.57 seconds |
| Started | Sep 24 05:55:39 AM UTC 24 |
| Finished | Sep 24 06:18:43 AM UTC 24 |
| Peak memory | 203024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646019774 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1646019774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/190.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.742548512 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 143634517698 ps |
| CPU time | 273.57 seconds |
| Started | Sep 24 05:55:46 AM UTC 24 |
| Finished | Sep 24 06:00:24 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742548512 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.742548512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/192.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.1900461749 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 75225051817 ps |
| CPU time | 275.79 seconds |
| Started | Sep 24 05:56:11 AM UTC 24 |
| Finished | Sep 24 06:00:51 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900461749 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1900461749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/195.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.3632695104 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 200396164661 ps |
| CPU time | 1091.04 seconds |
| Started | Sep 24 05:56:42 AM UTC 24 |
| Finished | Sep 24 06:15:06 AM UTC 24 |
| Peak memory | 202764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632695104 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3632695104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/196.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.1883989523 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 76076892668 ps |
| CPU time | 34.24 seconds |
| Started | Sep 24 05:56:48 AM UTC 24 |
| Finished | Sep 24 05:57:24 AM UTC 24 |
| Peak memory | 201004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883989523 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1883989523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/197.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.4098745460 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 81795063480 ps |
| CPU time | 260.51 seconds |
| Started | Sep 24 05:56:53 AM UTC 24 |
| Finished | Sep 24 06:01:18 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098745460 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4098745460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/198.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.1660238215 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 361461867213 ps |
| CPU time | 244.86 seconds |
| Started | Sep 24 05:13:03 AM UTC 24 |
| Finished | Sep 24 05:17:11 AM UTC 24 |
| Peak memory | 201252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660238215 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.1660238215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.4185600537 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 118777407410 ps |
| CPU time | 232.51 seconds |
| Started | Sep 24 05:13:02 AM UTC 24 |
| Finished | Sep 24 05:16:58 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185600537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.4185600537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.3413176950 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 154209653840 ps |
| CPU time | 206.73 seconds |
| Started | Sep 24 05:13:06 AM UTC 24 |
| Finished | Sep 24 05:16:37 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413176950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3413176950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.1143086666 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 201165730 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 05:13:08 AM UTC 24 |
| Finished | Sep 24 05:13:10 AM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143086666 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1143086666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.2186543755 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 31886666522 ps |
| CPU time | 19.13 seconds |
| Started | Sep 24 05:13:08 AM UTC 24 |
| Finished | Sep 24 05:13:28 AM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186543755 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.2186543755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/2.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.4252390673 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 150592270475 ps |
| CPU time | 48.37 seconds |
| Started | Sep 24 05:18:26 AM UTC 24 |
| Finished | Sep 24 05:19:16 AM UTC 24 |
| Peak memory | 201260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252390673 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.4252390673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.1316324356 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 889866552887 ps |
| CPU time | 208.32 seconds |
| Started | Sep 24 05:18:23 AM UTC 24 |
| Finished | Sep 24 05:21:55 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316324356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1316324356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/20.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.3839617669 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 111800369627 ps |
| CPU time | 322.81 seconds |
| Started | Sep 24 05:18:22 AM UTC 24 |
| Finished | Sep 24 05:23:49 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839617669 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3839617669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/20.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.3295419156 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 384675794408 ps |
| CPU time | 128.25 seconds |
| Started | Sep 24 05:18:32 AM UTC 24 |
| Finished | Sep 24 05:20:43 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295419156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3295419156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/20.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.32361924 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2665974906538 ps |
| CPU time | 671.06 seconds |
| Started | Sep 24 05:18:41 AM UTC 24 |
| Finished | Sep 24 05:30:00 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32361924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.32361924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.3932464415 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 155167604798 ps |
| CPU time | 360.57 seconds |
| Started | Sep 24 05:18:39 AM UTC 24 |
| Finished | Sep 24 05:24:44 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932464415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3932464415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/21.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.3741019250 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 849199642599 ps |
| CPU time | 839.46 seconds |
| Started | Sep 24 05:18:35 AM UTC 24 |
| Finished | Sep 24 05:32:45 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741019250 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3741019250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/21.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.1731048769 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 50762415163 ps |
| CPU time | 116.3 seconds |
| Started | Sep 24 05:18:43 AM UTC 24 |
| Finished | Sep 24 05:20:41 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731048769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1731048769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/21.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all_with_rand_reset.4035916107 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1131198492 ps |
| CPU time | 13.17 seconds |
| Started | Sep 24 05:18:44 AM UTC 24 |
| Finished | Sep 24 05:18:58 AM UTC 24 |
| Peak memory | 203172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4035916107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.rv_timer_stress_all_with_rand_reset.4035916107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/21.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.630337096 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 607723156971 ps |
| CPU time | 435.76 seconds |
| Started | Sep 24 05:18:59 AM UTC 24 |
| Finished | Sep 24 05:26:21 AM UTC 24 |
| Peak memory | 201248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630337096 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.630337096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.1308296272 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 505736556768 ps |
| CPU time | 438.52 seconds |
| Started | Sep 24 05:18:47 AM UTC 24 |
| Finished | Sep 24 05:26:12 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308296272 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1308296272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/22.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all_with_rand_reset.3078959527 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 860750002 ps |
| CPU time | 12.1 seconds |
| Started | Sep 24 05:19:14 AM UTC 24 |
| Finished | Sep 24 05:19:28 AM UTC 24 |
| Peak memory | 205164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3078959527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.rv_timer_stress_all_with_rand_reset.3078959527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/22.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.1746776487 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1214250519889 ps |
| CPU time | 600.41 seconds |
| Started | Sep 24 05:19:41 AM UTC 24 |
| Finished | Sep 24 05:29:49 AM UTC 24 |
| Peak memory | 201260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746776487 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.1746776487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.752838462 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 615063388987 ps |
| CPU time | 305.79 seconds |
| Started | Sep 24 05:19:29 AM UTC 24 |
| Finished | Sep 24 05:24:39 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752838462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.752838462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/23.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.3466854383 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 511092744842 ps |
| CPU time | 934.5 seconds |
| Started | Sep 24 05:19:19 AM UTC 24 |
| Finished | Sep 24 05:35:04 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466854383 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3466854383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/23.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.1394883399 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 28126213226 ps |
| CPU time | 52.06 seconds |
| Started | Sep 24 05:19:48 AM UTC 24 |
| Finished | Sep 24 05:20:42 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394883399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1394883399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/23.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.1556929631 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 191698673689 ps |
| CPU time | 251.81 seconds |
| Started | Sep 24 05:20:09 AM UTC 24 |
| Finished | Sep 24 05:24:25 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556929631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1556929631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/24.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.4267950996 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 26017922725 ps |
| CPU time | 64.01 seconds |
| Started | Sep 24 05:20:07 AM UTC 24 |
| Finished | Sep 24 05:21:13 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267950996 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.4267950996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/24.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.468472701 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 36586950727 ps |
| CPU time | 100.31 seconds |
| Started | Sep 24 05:20:18 AM UTC 24 |
| Finished | Sep 24 05:22:01 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468472701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.468472701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/24.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.1706815743 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1226482997592 ps |
| CPU time | 1787.23 seconds |
| Started | Sep 24 05:20:43 AM UTC 24 |
| Finished | Sep 24 05:50:51 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706815743 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.1706815743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/24.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.2104689962 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 500025467129 ps |
| CPU time | 1003.12 seconds |
| Started | Sep 24 05:20:45 AM UTC 24 |
| Finished | Sep 24 05:37:40 AM UTC 24 |
| Peak memory | 201260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104689962 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.2104689962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.2381148933 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 5258978975 ps |
| CPU time | 9.18 seconds |
| Started | Sep 24 05:20:54 AM UTC 24 |
| Finished | Sep 24 05:21:04 AM UTC 24 |
| Peak memory | 200928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381148933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2381148933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/25.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all_with_rand_reset.170400720 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1590863487 ps |
| CPU time | 22.34 seconds |
| Started | Sep 24 05:20:54 AM UTC 24 |
| Finished | Sep 24 05:21:18 AM UTC 24 |
| Peak memory | 205444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=170400720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.170400720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/25.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.1162919153 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 320511056907 ps |
| CPU time | 229.73 seconds |
| Started | Sep 24 05:21:13 AM UTC 24 |
| Finished | Sep 24 05:25:07 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162919153 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.1162919153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.4166449684 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 209566938516 ps |
| CPU time | 340.01 seconds |
| Started | Sep 24 05:21:05 AM UTC 24 |
| Finished | Sep 24 05:26:50 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166449684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.4166449684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/26.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.3421465756 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 375316230064 ps |
| CPU time | 326.61 seconds |
| Started | Sep 24 05:21:02 AM UTC 24 |
| Finished | Sep 24 05:26:33 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421465756 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3421465756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/26.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.1199822522 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 163289007 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 05:21:17 AM UTC 24 |
| Finished | Sep 24 05:21:20 AM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199822522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1199822522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/26.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.3194998159 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 386170967760 ps |
| CPU time | 589.49 seconds |
| Started | Sep 24 05:21:21 AM UTC 24 |
| Finished | Sep 24 05:31:17 AM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194998159 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.3194998159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/26.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.2439349745 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 240403916341 ps |
| CPU time | 537.78 seconds |
| Started | Sep 24 05:21:50 AM UTC 24 |
| Finished | Sep 24 05:30:55 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439349745 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.2439349745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.1777473793 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 188758248986 ps |
| CPU time | 322.47 seconds |
| Started | Sep 24 05:21:45 AM UTC 24 |
| Finished | Sep 24 05:27:11 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777473793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1777473793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/27.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.3164341593 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 330997303401 ps |
| CPU time | 404.68 seconds |
| Started | Sep 24 05:21:52 AM UTC 24 |
| Finished | Sep 24 05:28:42 AM UTC 24 |
| Peak memory | 201284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164341593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3164341593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/27.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.3797129666 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 255638556683 ps |
| CPU time | 194.34 seconds |
| Started | Sep 24 05:22:23 AM UTC 24 |
| Finished | Sep 24 05:25:41 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797129666 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.3797129666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.2350873225 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 10750302325 ps |
| CPU time | 22.64 seconds |
| Started | Sep 24 05:22:11 AM UTC 24 |
| Finished | Sep 24 05:22:35 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350873225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2350873225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/28.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.594527705 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 193173141456 ps |
| CPU time | 476.12 seconds |
| Started | Sep 24 05:22:25 AM UTC 24 |
| Finished | Sep 24 05:30:28 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594527705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.594527705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/28.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.957464436 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 240480196021 ps |
| CPU time | 200.84 seconds |
| Started | Sep 24 05:22:49 AM UTC 24 |
| Finished | Sep 24 05:26:13 AM UTC 24 |
| Peak memory | 200984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957464436 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.957464436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.2710438029 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 343667864344 ps |
| CPU time | 270.8 seconds |
| Started | Sep 24 05:22:42 AM UTC 24 |
| Finished | Sep 24 05:27:16 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710438029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2710438029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/29.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.1790714365 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 37230736707 ps |
| CPU time | 59.61 seconds |
| Started | Sep 24 05:22:36 AM UTC 24 |
| Finished | Sep 24 05:23:37 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790714365 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1790714365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/29.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.4067920333 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 56153666866 ps |
| CPU time | 47.63 seconds |
| Started | Sep 24 05:23:05 AM UTC 24 |
| Finished | Sep 24 05:23:54 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067920333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.4067920333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/29.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.1852489375 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2523667341072 ps |
| CPU time | 754.39 seconds |
| Started | Sep 24 05:13:21 AM UTC 24 |
| Finished | Sep 24 05:26:05 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852489375 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.1852489375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.2705463908 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 609624613270 ps |
| CPU time | 258.07 seconds |
| Started | Sep 24 05:13:12 AM UTC 24 |
| Finished | Sep 24 05:17:33 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705463908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2705463908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.3874846280 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 123167871759 ps |
| CPU time | 168.53 seconds |
| Started | Sep 24 05:13:09 AM UTC 24 |
| Finished | Sep 24 05:16:01 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874846280 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3874846280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.2176123548 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2563446956 ps |
| CPU time | 4.11 seconds |
| Started | Sep 24 05:13:23 AM UTC 24 |
| Finished | Sep 24 05:13:28 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176123548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2176123548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.2587201374 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 65123226 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 05:13:29 AM UTC 24 |
| Finished | Sep 24 05:13:32 AM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587201374 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2587201374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.761194473 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 111282011 ps |
| CPU time | 0.82 seconds |
| Started | Sep 24 05:13:28 AM UTC 24 |
| Finished | Sep 24 05:13:30 AM UTC 24 |
| Peak memory | 199484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761194473 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.761194473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/3.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.3706574353 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 31199979274 ps |
| CPU time | 16.96 seconds |
| Started | Sep 24 05:23:37 AM UTC 24 |
| Finished | Sep 24 05:23:55 AM UTC 24 |
| Peak memory | 201324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706574353 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.3706574353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.2696123406 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 151499026810 ps |
| CPU time | 301.42 seconds |
| Started | Sep 24 05:23:28 AM UTC 24 |
| Finished | Sep 24 05:28:34 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696123406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2696123406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/30.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.3376179632 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 177547572428 ps |
| CPU time | 353.4 seconds |
| Started | Sep 24 05:23:20 AM UTC 24 |
| Finished | Sep 24 05:29:19 AM UTC 24 |
| Peak memory | 201208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376179632 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3376179632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/30.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.1990983311 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 36413876 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 05:23:51 AM UTC 24 |
| Finished | Sep 24 05:23:52 AM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990983311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1990983311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/30.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all_with_rand_reset.978964606 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 12170092844 ps |
| CPU time | 65.49 seconds |
| Started | Sep 24 05:23:54 AM UTC 24 |
| Finished | Sep 24 05:25:01 AM UTC 24 |
| Peak memory | 205368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=978964606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.978964606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/30.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.3950941179 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 440017637814 ps |
| CPU time | 663.88 seconds |
| Started | Sep 24 05:24:05 AM UTC 24 |
| Finished | Sep 24 05:35:16 AM UTC 24 |
| Peak memory | 201020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950941179 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.3950941179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.2124848422 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 49470425745 ps |
| CPU time | 61.14 seconds |
| Started | Sep 24 05:23:57 AM UTC 24 |
| Finished | Sep 24 05:25:00 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124848422 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2124848422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/31.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.3481532405 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 188681535 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 05:24:26 AM UTC 24 |
| Finished | Sep 24 05:24:28 AM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481532405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3481532405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/31.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.1281223671 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 27058497 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 05:24:29 AM UTC 24 |
| Finished | Sep 24 05:24:31 AM UTC 24 |
| Peak memory | 199984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281223671 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.1281223671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/31.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.4102103914 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 912796651171 ps |
| CPU time | 837.16 seconds |
| Started | Sep 24 05:24:41 AM UTC 24 |
| Finished | Sep 24 05:38:48 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102103914 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.4102103914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.605376968 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 87124634604 ps |
| CPU time | 586.02 seconds |
| Started | Sep 24 05:24:32 AM UTC 24 |
| Finished | Sep 24 05:34:26 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605376968 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.605376968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/32.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.2871926924 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 13189608485 ps |
| CPU time | 37.63 seconds |
| Started | Sep 24 05:24:43 AM UTC 24 |
| Finished | Sep 24 05:25:22 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871926924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2871926924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/32.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.3419505103 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 301768201196 ps |
| CPU time | 687.69 seconds |
| Started | Sep 24 05:25:00 AM UTC 24 |
| Finished | Sep 24 05:36:37 AM UTC 24 |
| Peak memory | 201272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419505103 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.3419505103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/32.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all_with_rand_reset.3917764951 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 17485338983 ps |
| CPU time | 56.4 seconds |
| Started | Sep 24 05:24:45 AM UTC 24 |
| Finished | Sep 24 05:25:43 AM UTC 24 |
| Peak memory | 205288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3917764951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.rv_timer_stress_all_with_rand_reset.3917764951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/32.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.1163028152 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 53678594707 ps |
| CPU time | 68.33 seconds |
| Started | Sep 24 05:25:03 AM UTC 24 |
| Finished | Sep 24 05:26:13 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163028152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1163028152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/33.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.1131624251 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 41582097134 ps |
| CPU time | 130.68 seconds |
| Started | Sep 24 05:25:02 AM UTC 24 |
| Finished | Sep 24 05:27:15 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131624251 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1131624251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/33.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.338958540 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 87073577036 ps |
| CPU time | 167.52 seconds |
| Started | Sep 24 05:25:23 AM UTC 24 |
| Finished | Sep 24 05:28:13 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338958540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.338958540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/33.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.1632340338 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 961155897400 ps |
| CPU time | 652.85 seconds |
| Started | Sep 24 05:25:31 AM UTC 24 |
| Finished | Sep 24 05:36:32 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632340338 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.1632340338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/33.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.1707044385 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 22695185276 ps |
| CPU time | 36.57 seconds |
| Started | Sep 24 05:25:40 AM UTC 24 |
| Finished | Sep 24 05:26:18 AM UTC 24 |
| Peak memory | 201000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707044385 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.1707044385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.2622819870 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 161832384998 ps |
| CPU time | 461.93 seconds |
| Started | Sep 24 05:25:33 AM UTC 24 |
| Finished | Sep 24 05:33:21 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622819870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2622819870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/34.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.1309045880 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 656689463101 ps |
| CPU time | 2933.44 seconds |
| Started | Sep 24 05:25:33 AM UTC 24 |
| Finished | Sep 24 06:15:00 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309045880 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1309045880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/34.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.49584521 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 44532522722 ps |
| CPU time | 110.72 seconds |
| Started | Sep 24 05:25:41 AM UTC 24 |
| Finished | Sep 24 05:27:34 AM UTC 24 |
| Peak memory | 201280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49584521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.49584521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/34.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.631157822 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 448948658045 ps |
| CPU time | 692.65 seconds |
| Started | Sep 24 05:26:14 AM UTC 24 |
| Finished | Sep 24 05:37:55 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631157822 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.631157822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.4091484140 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 670076513714 ps |
| CPU time | 337.72 seconds |
| Started | Sep 24 05:26:13 AM UTC 24 |
| Finished | Sep 24 05:31:55 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091484140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4091484140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/35.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.2726864841 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 624874031984 ps |
| CPU time | 409.25 seconds |
| Started | Sep 24 05:26:06 AM UTC 24 |
| Finished | Sep 24 05:33:00 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726864841 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2726864841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/35.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.2673217794 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 292310265775 ps |
| CPU time | 915.95 seconds |
| Started | Sep 24 05:26:22 AM UTC 24 |
| Finished | Sep 24 05:41:48 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673217794 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.2673217794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/35.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.3263505273 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 267222568859 ps |
| CPU time | 606.69 seconds |
| Started | Sep 24 05:26:51 AM UTC 24 |
| Finished | Sep 24 05:37:06 AM UTC 24 |
| Peak memory | 201004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263505273 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.3263505273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.2417957703 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 561395068696 ps |
| CPU time | 161.61 seconds |
| Started | Sep 24 05:26:48 AM UTC 24 |
| Finished | Sep 24 05:29:33 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417957703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2417957703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/36.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.1070094957 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 409180837080 ps |
| CPU time | 1908.79 seconds |
| Started | Sep 24 05:26:34 AM UTC 24 |
| Finished | Sep 24 05:58:46 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070094957 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1070094957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/36.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all_with_rand_reset.3462428321 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9512609902 ps |
| CPU time | 29.52 seconds |
| Started | Sep 24 05:27:12 AM UTC 24 |
| Finished | Sep 24 05:27:43 AM UTC 24 |
| Peak memory | 205360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3462428321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.rv_timer_stress_all_with_rand_reset.3462428321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/36.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.2649940415 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 255882140983 ps |
| CPU time | 114.65 seconds |
| Started | Sep 24 05:27:37 AM UTC 24 |
| Finished | Sep 24 05:29:34 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649940415 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.2649940415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.1295581526 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 95853903068 ps |
| CPU time | 307.44 seconds |
| Started | Sep 24 05:27:17 AM UTC 24 |
| Finished | Sep 24 05:32:28 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295581526 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1295581526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/37.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.2718754043 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 139085795537 ps |
| CPU time | 117.28 seconds |
| Started | Sep 24 05:27:44 AM UTC 24 |
| Finished | Sep 24 05:29:44 AM UTC 24 |
| Peak memory | 201408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718754043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2718754043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/37.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.1225149126 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 232424937161 ps |
| CPU time | 1204.17 seconds |
| Started | Sep 24 05:28:17 AM UTC 24 |
| Finished | Sep 24 05:48:35 AM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225149126 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.1225149126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/37.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.3107147706 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 553988510225 ps |
| CPU time | 381.44 seconds |
| Started | Sep 24 05:28:36 AM UTC 24 |
| Finished | Sep 24 05:35:03 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107147706 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.3107147706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.2604191827 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 308406117326 ps |
| CPU time | 160.33 seconds |
| Started | Sep 24 05:28:35 AM UTC 24 |
| Finished | Sep 24 05:31:18 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604191827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2604191827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/38.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.1330651637 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 286212675708 ps |
| CPU time | 254.88 seconds |
| Started | Sep 24 05:28:31 AM UTC 24 |
| Finished | Sep 24 05:32:50 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330651637 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1330651637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/38.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.363106496 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 122662996 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 05:28:42 AM UTC 24 |
| Finished | Sep 24 05:28:45 AM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363106496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.363106496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/38.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.1696345908 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 867356242864 ps |
| CPU time | 742.65 seconds |
| Started | Sep 24 05:28:55 AM UTC 24 |
| Finished | Sep 24 05:41:27 AM UTC 24 |
| Peak memory | 201020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696345908 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.1696345908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/38.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.1484167233 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 343911788475 ps |
| CPU time | 244.39 seconds |
| Started | Sep 24 05:29:20 AM UTC 24 |
| Finished | Sep 24 05:33:28 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484167233 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.1484167233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.965608672 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 53954775988 ps |
| CPU time | 118.91 seconds |
| Started | Sep 24 05:29:01 AM UTC 24 |
| Finished | Sep 24 05:31:03 AM UTC 24 |
| Peak memory | 201216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965608672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.965608672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/39.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.2490979985 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 329074004721 ps |
| CPU time | 154.6 seconds |
| Started | Sep 24 05:29:01 AM UTC 24 |
| Finished | Sep 24 05:31:39 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490979985 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2490979985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/39.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.3349093999 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 364947917418 ps |
| CPU time | 100.98 seconds |
| Started | Sep 24 05:29:26 AM UTC 24 |
| Finished | Sep 24 05:31:09 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349093999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3349093999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/39.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.1682880207 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1085362663169 ps |
| CPU time | 242.3 seconds |
| Started | Sep 24 05:29:36 AM UTC 24 |
| Finished | Sep 24 05:33:42 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682880207 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.1682880207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/39.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.3583204145 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1404517321366 ps |
| CPU time | 324.29 seconds |
| Started | Sep 24 05:13:35 AM UTC 24 |
| Finished | Sep 24 05:19:03 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583204145 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.3583204145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.3514225797 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 418104294513 ps |
| CPU time | 197.21 seconds |
| Started | Sep 24 05:13:32 AM UTC 24 |
| Finished | Sep 24 05:16:53 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514225797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3514225797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.246807705 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 22538606163 ps |
| CPU time | 56.96 seconds |
| Started | Sep 24 05:13:36 AM UTC 24 |
| Finished | Sep 24 05:14:35 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246807705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.246807705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.3065207030 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 158560087 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 05:13:48 AM UTC 24 |
| Finished | Sep 24 05:13:51 AM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065207030 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3065207030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.3443151356 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1025674656136 ps |
| CPU time | 163.38 seconds |
| Started | Sep 24 05:13:46 AM UTC 24 |
| Finished | Sep 24 05:16:32 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443151356 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.3443151356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/4.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.1643644942 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 357860066106 ps |
| CPU time | 172.79 seconds |
| Started | Sep 24 05:29:46 AM UTC 24 |
| Finished | Sep 24 05:32:42 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643644942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1643644942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/40.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.2566137364 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 195397769944 ps |
| CPU time | 2005.87 seconds |
| Started | Sep 24 05:29:42 AM UTC 24 |
| Finished | Sep 24 06:03:31 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566137364 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2566137364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/40.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.3423131347 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 274179777514 ps |
| CPU time | 218.49 seconds |
| Started | Sep 24 05:29:50 AM UTC 24 |
| Finished | Sep 24 05:33:32 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423131347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3423131347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/40.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.3411327455 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 936426123739 ps |
| CPU time | 945.26 seconds |
| Started | Sep 24 05:30:13 AM UTC 24 |
| Finished | Sep 24 05:46:09 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411327455 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.3411327455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/40.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.3523703910 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 21347936061 ps |
| CPU time | 33.64 seconds |
| Started | Sep 24 05:30:29 AM UTC 24 |
| Finished | Sep 24 05:31:04 AM UTC 24 |
| Peak memory | 201348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523703910 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.3523703910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.2500717936 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 58316688114 ps |
| CPU time | 134.15 seconds |
| Started | Sep 24 05:30:27 AM UTC 24 |
| Finished | Sep 24 05:32:43 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500717936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2500717936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/41.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.2174174361 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 782164402731 ps |
| CPU time | 423.69 seconds |
| Started | Sep 24 05:31:03 AM UTC 24 |
| Finished | Sep 24 05:38:12 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174174361 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.2174174361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/41.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all_with_rand_reset.1017884998 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 5172128051 ps |
| CPU time | 17.71 seconds |
| Started | Sep 24 05:30:55 AM UTC 24 |
| Finished | Sep 24 05:31:14 AM UTC 24 |
| Peak memory | 201456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1017884998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.rv_timer_stress_all_with_rand_reset.1017884998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/41.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.576974448 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 554025326236 ps |
| CPU time | 323.45 seconds |
| Started | Sep 24 05:31:15 AM UTC 24 |
| Finished | Sep 24 05:36:43 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576974448 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.576974448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.1241514706 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 504676250620 ps |
| CPU time | 239.43 seconds |
| Started | Sep 24 05:31:10 AM UTC 24 |
| Finished | Sep 24 05:35:13 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241514706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1241514706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/42.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.4129183420 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 227787888006 ps |
| CPU time | 108.56 seconds |
| Started | Sep 24 05:31:04 AM UTC 24 |
| Finished | Sep 24 05:32:55 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129183420 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4129183420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/42.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.1598574287 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 17443908806 ps |
| CPU time | 13.79 seconds |
| Started | Sep 24 05:31:17 AM UTC 24 |
| Finished | Sep 24 05:31:32 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598574287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1598574287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/42.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.3457972660 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 247907022221 ps |
| CPU time | 483.43 seconds |
| Started | Sep 24 05:31:40 AM UTC 24 |
| Finished | Sep 24 05:39:49 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457972660 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.3457972660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.2954060286 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 55625448362 ps |
| CPU time | 86.83 seconds |
| Started | Sep 24 05:31:33 AM UTC 24 |
| Finished | Sep 24 05:33:02 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954060286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2954060286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/43.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.3721293376 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 157011862121 ps |
| CPU time | 121.91 seconds |
| Started | Sep 24 05:31:30 AM UTC 24 |
| Finished | Sep 24 05:33:34 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721293376 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3721293376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/43.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.1287764269 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1047788477 ps |
| CPU time | 5.92 seconds |
| Started | Sep 24 05:31:41 AM UTC 24 |
| Finished | Sep 24 05:31:48 AM UTC 24 |
| Peak memory | 201088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287764269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1287764269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/43.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.3396713720 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 55514650480 ps |
| CPU time | 122.38 seconds |
| Started | Sep 24 05:32:29 AM UTC 24 |
| Finished | Sep 24 05:34:34 AM UTC 24 |
| Peak memory | 201020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396713720 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.3396713720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.39216922 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 205375832990 ps |
| CPU time | 224.97 seconds |
| Started | Sep 24 05:32:16 AM UTC 24 |
| Finished | Sep 24 05:36:04 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39216922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.39216922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/44.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.1249241921 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 498420856579 ps |
| CPU time | 307.88 seconds |
| Started | Sep 24 05:31:56 AM UTC 24 |
| Finished | Sep 24 05:37:08 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249241921 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1249241921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/44.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.2564083889 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 230598674106 ps |
| CPU time | 414.65 seconds |
| Started | Sep 24 05:32:51 AM UTC 24 |
| Finished | Sep 24 05:39:51 AM UTC 24 |
| Peak memory | 201260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564083889 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.2564083889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.3750678115 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 474773221994 ps |
| CPU time | 273.98 seconds |
| Started | Sep 24 05:32:48 AM UTC 24 |
| Finished | Sep 24 05:37:26 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750678115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3750678115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/45.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.1840017815 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 120866164867 ps |
| CPU time | 123.33 seconds |
| Started | Sep 24 05:32:55 AM UTC 24 |
| Finished | Sep 24 05:35:01 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840017815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1840017815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/45.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.3188867178 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 520552116196 ps |
| CPU time | 585.98 seconds |
| Started | Sep 24 05:33:01 AM UTC 24 |
| Finished | Sep 24 05:42:54 AM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188867178 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.3188867178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/45.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.828118906 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2009238320846 ps |
| CPU time | 1123.67 seconds |
| Started | Sep 24 05:33:28 AM UTC 24 |
| Finished | Sep 24 05:52:25 AM UTC 24 |
| Peak memory | 200984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828118906 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.828118906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.356295488 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 152730261221 ps |
| CPU time | 415.95 seconds |
| Started | Sep 24 05:33:22 AM UTC 24 |
| Finished | Sep 24 05:40:23 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356295488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.356295488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/46.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.1153719811 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 161712622313 ps |
| CPU time | 142.72 seconds |
| Started | Sep 24 05:33:02 AM UTC 24 |
| Finished | Sep 24 05:35:28 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153719811 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1153719811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/46.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.670864991 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 939684075 ps |
| CPU time | 3.97 seconds |
| Started | Sep 24 05:33:31 AM UTC 24 |
| Finished | Sep 24 05:33:37 AM UTC 24 |
| Peak memory | 200860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670864991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.670864991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/46.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.2731513435 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 117737862636 ps |
| CPU time | 209.98 seconds |
| Started | Sep 24 05:33:43 AM UTC 24 |
| Finished | Sep 24 05:37:16 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731513435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2731513435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/47.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.470379035 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 124011237254 ps |
| CPU time | 135.59 seconds |
| Started | Sep 24 05:33:57 AM UTC 24 |
| Finished | Sep 24 05:36:15 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470379035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.470379035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/47.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.3295733621 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 163708900726 ps |
| CPU time | 707.84 seconds |
| Started | Sep 24 05:34:27 AM UTC 24 |
| Finished | Sep 24 05:46:23 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295733621 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.3295733621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/47.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.1046414147 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 368769406135 ps |
| CPU time | 593.98 seconds |
| Started | Sep 24 05:35:01 AM UTC 24 |
| Finished | Sep 24 05:45:02 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046414147 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.1046414147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.2911830927 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 72890148508 ps |
| CPU time | 92.72 seconds |
| Started | Sep 24 05:34:35 AM UTC 24 |
| Finished | Sep 24 05:36:10 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911830927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2911830927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/48.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.3246674745 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1989241515605 ps |
| CPU time | 1620.35 seconds |
| Started | Sep 24 05:34:35 AM UTC 24 |
| Finished | Sep 24 06:01:54 AM UTC 24 |
| Peak memory | 202768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246674745 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3246674745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/48.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.3433531640 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 105063678472 ps |
| CPU time | 146.29 seconds |
| Started | Sep 24 05:35:04 AM UTC 24 |
| Finished | Sep 24 05:37:33 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433531640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3433531640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/48.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.3497594597 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4074025380745 ps |
| CPU time | 1118.93 seconds |
| Started | Sep 24 05:35:09 AM UTC 24 |
| Finished | Sep 24 05:54:01 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497594597 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.3497594597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/48.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all_with_rand_reset.2970421462 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 8473398522 ps |
| CPU time | 37.97 seconds |
| Started | Sep 24 05:35:05 AM UTC 24 |
| Finished | Sep 24 05:35:44 AM UTC 24 |
| Peak memory | 205488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2970421462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.rv_timer_stress_all_with_rand_reset.2970421462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/48.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.2110021193 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 295888601001 ps |
| CPU time | 453.43 seconds |
| Started | Sep 24 05:35:17 AM UTC 24 |
| Finished | Sep 24 05:42:56 AM UTC 24 |
| Peak memory | 201092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110021193 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.2110021193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.2364692780 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 84535041147 ps |
| CPU time | 173.21 seconds |
| Started | Sep 24 05:35:14 AM UTC 24 |
| Finished | Sep 24 05:38:10 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364692780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2364692780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/49.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.1904761178 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 275819515491 ps |
| CPU time | 314.57 seconds |
| Started | Sep 24 05:35:10 AM UTC 24 |
| Finished | Sep 24 05:40:29 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904761178 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1904761178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/49.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.2421067950 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 277962610099 ps |
| CPU time | 218.6 seconds |
| Started | Sep 24 05:35:29 AM UTC 24 |
| Finished | Sep 24 05:39:11 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421067950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2421067950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/49.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all_with_rand_reset.324301197 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7771046267 ps |
| CPU time | 25.79 seconds |
| Started | Sep 24 05:35:45 AM UTC 24 |
| Finished | Sep 24 05:36:12 AM UTC 24 |
| Peak memory | 205296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=324301197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.324301197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/49.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.3669704764 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 133821992282 ps |
| CPU time | 123.38 seconds |
| Started | Sep 24 05:13:55 AM UTC 24 |
| Finished | Sep 24 05:16:00 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669704764 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.3669704764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.1010947020 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 67620132550 ps |
| CPU time | 123.2 seconds |
| Started | Sep 24 05:13:52 AM UTC 24 |
| Finished | Sep 24 05:15:57 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010947020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1010947020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/5.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.3216164207 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 74070726208 ps |
| CPU time | 44.84 seconds |
| Started | Sep 24 05:13:52 AM UTC 24 |
| Finished | Sep 24 05:14:38 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216164207 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3216164207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/5.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.3666090606 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3915117709 ps |
| CPU time | 25.38 seconds |
| Started | Sep 24 05:13:56 AM UTC 24 |
| Finished | Sep 24 05:14:23 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666090606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3666090606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/5.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.3596670917 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1645440357579 ps |
| CPU time | 1104.92 seconds |
| Started | Sep 24 05:14:10 AM UTC 24 |
| Finished | Sep 24 05:32:47 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596670917 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.3596670917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/5.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all_with_rand_reset.2500991736 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5718127189 ps |
| CPU time | 31.98 seconds |
| Started | Sep 24 05:14:08 AM UTC 24 |
| Finished | Sep 24 05:14:42 AM UTC 24 |
| Peak memory | 205296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2500991736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.rv_timer_stress_all_with_rand_reset.2500991736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.2717125048 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 118065045010 ps |
| CPU time | 362.55 seconds |
| Started | Sep 24 05:36:10 AM UTC 24 |
| Finished | Sep 24 05:42:18 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717125048 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2717125048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/51.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.604741250 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 42983738257 ps |
| CPU time | 288.13 seconds |
| Started | Sep 24 05:36:11 AM UTC 24 |
| Finished | Sep 24 05:41:04 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604741250 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.604741250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/52.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.3328738744 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 117277010450 ps |
| CPU time | 88.37 seconds |
| Started | Sep 24 05:36:12 AM UTC 24 |
| Finished | Sep 24 05:37:43 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328738744 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3328738744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/53.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.2630949589 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 109907813970 ps |
| CPU time | 462.8 seconds |
| Started | Sep 24 05:36:16 AM UTC 24 |
| Finished | Sep 24 05:44:04 AM UTC 24 |
| Peak memory | 201008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630949589 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2630949589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/54.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.843450371 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 176774993538 ps |
| CPU time | 380.41 seconds |
| Started | Sep 24 05:36:33 AM UTC 24 |
| Finished | Sep 24 05:42:58 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843450371 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.843450371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/55.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.498949009 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 69054366668 ps |
| CPU time | 107.18 seconds |
| Started | Sep 24 05:36:38 AM UTC 24 |
| Finished | Sep 24 05:38:27 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498949009 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.498949009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/56.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.1078110577 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 75079747871 ps |
| CPU time | 108.33 seconds |
| Started | Sep 24 05:37:10 AM UTC 24 |
| Finished | Sep 24 05:39:01 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078110577 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1078110577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/59.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.1429158033 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 273562547461 ps |
| CPU time | 172 seconds |
| Started | Sep 24 05:14:14 AM UTC 24 |
| Finished | Sep 24 05:17:09 AM UTC 24 |
| Peak memory | 201060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429158033 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.1429158033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.1670372899 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 92713981635 ps |
| CPU time | 463.37 seconds |
| Started | Sep 24 05:14:14 AM UTC 24 |
| Finished | Sep 24 05:22:03 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670372899 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1670372899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/6.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.3132532864 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 176286980841 ps |
| CPU time | 192.08 seconds |
| Started | Sep 24 05:14:15 AM UTC 24 |
| Finished | Sep 24 05:17:30 AM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132532864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3132532864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/6.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.2535370738 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 339130200030 ps |
| CPU time | 262.86 seconds |
| Started | Sep 24 05:37:12 AM UTC 24 |
| Finished | Sep 24 05:41:40 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535370738 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2535370738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/60.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.118094340 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 442825070571 ps |
| CPU time | 306.76 seconds |
| Started | Sep 24 05:37:16 AM UTC 24 |
| Finished | Sep 24 05:42:27 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118094340 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.118094340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/61.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.1710914509 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2372360311240 ps |
| CPU time | 1820.85 seconds |
| Started | Sep 24 05:37:26 AM UTC 24 |
| Finished | Sep 24 06:08:11 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710914509 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1710914509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/63.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.3833176287 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 61904052280 ps |
| CPU time | 226.27 seconds |
| Started | Sep 24 05:37:34 AM UTC 24 |
| Finished | Sep 24 05:41:24 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833176287 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3833176287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/64.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.2837731877 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 77071353593 ps |
| CPU time | 306.67 seconds |
| Started | Sep 24 05:37:41 AM UTC 24 |
| Finished | Sep 24 05:42:51 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837731877 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2837731877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/65.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.1508699040 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 116344332651 ps |
| CPU time | 1468.88 seconds |
| Started | Sep 24 05:37:44 AM UTC 24 |
| Finished | Sep 24 06:02:31 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508699040 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1508699040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/66.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.4239182284 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 276936425198 ps |
| CPU time | 317.07 seconds |
| Started | Sep 24 05:37:56 AM UTC 24 |
| Finished | Sep 24 05:43:17 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239182284 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4239182284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/68.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.306509276 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 85690238079 ps |
| CPU time | 122.31 seconds |
| Started | Sep 24 05:38:11 AM UTC 24 |
| Finished | Sep 24 05:40:16 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306509276 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.306509276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/69.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.1993656753 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 77406004410 ps |
| CPU time | 76.72 seconds |
| Started | Sep 24 05:14:23 AM UTC 24 |
| Finished | Sep 24 05:15:42 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993656753 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.1993656753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.1009072842 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 526787205292 ps |
| CPU time | 245.4 seconds |
| Started | Sep 24 05:14:22 AM UTC 24 |
| Finished | Sep 24 05:18:31 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009072842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1009072842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/7.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.942280134 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 31054367036 ps |
| CPU time | 41.5 seconds |
| Started | Sep 24 05:14:22 AM UTC 24 |
| Finished | Sep 24 05:15:05 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942280134 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.942280134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/7.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.4258070668 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 158110676219 ps |
| CPU time | 103.71 seconds |
| Started | Sep 24 05:14:29 AM UTC 24 |
| Finished | Sep 24 05:16:15 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258070668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.4258070668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/7.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.3674220514 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 507895756677 ps |
| CPU time | 879.01 seconds |
| Started | Sep 24 05:14:34 AM UTC 24 |
| Finished | Sep 24 05:29:23 AM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674220514 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.3674220514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/7.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all_with_rand_reset.1126987761 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 456295291 ps |
| CPU time | 2.68 seconds |
| Started | Sep 24 05:14:31 AM UTC 24 |
| Finished | Sep 24 05:14:35 AM UTC 24 |
| Peak memory | 203448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1126987761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.rv_timer_stress_all_with_rand_reset.1126987761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/7.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.3730630232 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 136464788761 ps |
| CPU time | 210.15 seconds |
| Started | Sep 24 05:38:13 AM UTC 24 |
| Finished | Sep 24 05:41:46 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730630232 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3730630232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/70.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.1616811720 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 40791033 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 05:38:28 AM UTC 24 |
| Finished | Sep 24 05:38:30 AM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616811720 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1616811720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/71.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.898453031 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 140583470048 ps |
| CPU time | 614.54 seconds |
| Started | Sep 24 05:38:49 AM UTC 24 |
| Finished | Sep 24 05:49:11 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898453031 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.898453031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/73.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.928433655 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 154312581056 ps |
| CPU time | 307.93 seconds |
| Started | Sep 24 05:39:01 AM UTC 24 |
| Finished | Sep 24 05:44:13 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928433655 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.928433655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/74.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.1816055155 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 523508519651 ps |
| CPU time | 524.59 seconds |
| Started | Sep 24 05:39:11 AM UTC 24 |
| Finished | Sep 24 05:48:03 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816055155 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1816055155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/75.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.1674538736 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 123831805322 ps |
| CPU time | 147.05 seconds |
| Started | Sep 24 05:39:33 AM UTC 24 |
| Finished | Sep 24 05:42:02 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674538736 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1674538736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/76.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.4046326785 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 225362639422 ps |
| CPU time | 477.11 seconds |
| Started | Sep 24 05:39:50 AM UTC 24 |
| Finished | Sep 24 05:47:53 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046326785 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4046326785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/77.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.2468609013 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 163662355186 ps |
| CPU time | 157.61 seconds |
| Started | Sep 24 05:39:52 AM UTC 24 |
| Finished | Sep 24 05:42:32 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468609013 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2468609013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/78.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.1006994811 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 158849510683 ps |
| CPU time | 136.52 seconds |
| Started | Sep 24 05:14:36 AM UTC 24 |
| Finished | Sep 24 05:16:55 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006994811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1006994811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/8.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.145571703 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 87846822304 ps |
| CPU time | 305.94 seconds |
| Started | Sep 24 05:14:39 AM UTC 24 |
| Finished | Sep 24 05:19:49 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145571703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.145571703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/8.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.853837365 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 135530377674 ps |
| CPU time | 518.3 seconds |
| Started | Sep 24 05:14:42 AM UTC 24 |
| Finished | Sep 24 05:23:27 AM UTC 24 |
| Peak memory | 201272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853837365 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.853837365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/8.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.2834819332 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 88055889228 ps |
| CPU time | 163.68 seconds |
| Started | Sep 24 05:40:17 AM UTC 24 |
| Finished | Sep 24 05:43:03 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834819332 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2834819332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/80.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.2081159184 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 409199492921 ps |
| CPU time | 390.61 seconds |
| Started | Sep 24 05:40:24 AM UTC 24 |
| Finished | Sep 24 05:47:00 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081159184 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2081159184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/81.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.1426455594 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 77170670370 ps |
| CPU time | 584.94 seconds |
| Started | Sep 24 05:40:29 AM UTC 24 |
| Finished | Sep 24 05:50:22 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426455594 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1426455594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/82.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.570460633 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 115624185678 ps |
| CPU time | 402.01 seconds |
| Started | Sep 24 05:41:04 AM UTC 24 |
| Finished | Sep 24 05:47:52 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570460633 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.570460633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/83.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.2462156749 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 196808649823 ps |
| CPU time | 920.11 seconds |
| Started | Sep 24 05:41:25 AM UTC 24 |
| Finished | Sep 24 05:56:56 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462156749 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2462156749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/85.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.1117409393 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 171917077839 ps |
| CPU time | 181.02 seconds |
| Started | Sep 24 05:41:28 AM UTC 24 |
| Finished | Sep 24 05:44:31 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117409393 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1117409393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/86.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.172820240 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 23203279927 ps |
| CPU time | 112.76 seconds |
| Started | Sep 24 05:41:48 AM UTC 24 |
| Finished | Sep 24 05:43:43 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172820240 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.172820240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/88.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.3364365620 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 274738328894 ps |
| CPU time | 366.6 seconds |
| Started | Sep 24 05:41:49 AM UTC 24 |
| Finished | Sep 24 05:48:01 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364365620 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3364365620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/89.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.3687960098 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 810685405595 ps |
| CPU time | 974.57 seconds |
| Started | Sep 24 05:14:58 AM UTC 24 |
| Finished | Sep 24 05:31:24 AM UTC 24 |
| Peak memory | 201252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687960098 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.3687960098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.22234689 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 50639176589 ps |
| CPU time | 113.32 seconds |
| Started | Sep 24 05:14:48 AM UTC 24 |
| Finished | Sep 24 05:16:44 AM UTC 24 |
| Peak memory | 201256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22234689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.22234689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/9.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.3222042700 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 89493026687 ps |
| CPU time | 205.17 seconds |
| Started | Sep 24 05:15:04 AM UTC 24 |
| Finished | Sep 24 05:18:32 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222042700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3222042700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/9.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.3166174800 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1302299861409 ps |
| CPU time | 898.34 seconds |
| Started | Sep 24 05:15:10 AM UTC 24 |
| Finished | Sep 24 05:30:19 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166174800 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.3166174800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/9.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.1205008533 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 54524222112 ps |
| CPU time | 312.26 seconds |
| Started | Sep 24 05:42:03 AM UTC 24 |
| Finished | Sep 24 05:47:20 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205008533 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1205008533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/90.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.2748445399 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 104565194115 ps |
| CPU time | 147.46 seconds |
| Started | Sep 24 05:42:18 AM UTC 24 |
| Finished | Sep 24 05:44:48 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748445399 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2748445399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/91.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.3949435753 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 242925886317 ps |
| CPU time | 309.29 seconds |
| Started | Sep 24 05:42:28 AM UTC 24 |
| Finished | Sep 24 05:47:42 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949435753 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3949435753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/92.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.2996887063 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 109926183492 ps |
| CPU time | 91.66 seconds |
| Started | Sep 24 05:42:33 AM UTC 24 |
| Finished | Sep 24 05:44:07 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996887063 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2996887063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/93.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.4006509748 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 54254471204 ps |
| CPU time | 215.4 seconds |
| Started | Sep 24 05:42:52 AM UTC 24 |
| Finished | Sep 24 05:46:31 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006509748 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.4006509748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/94.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.3060492453 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 138716437107 ps |
| CPU time | 3069.62 seconds |
| Started | Sep 24 05:42:54 AM UTC 24 |
| Finished | Sep 24 06:34:39 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060492453 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3060492453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/96.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.1509590471 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 84725085032 ps |
| CPU time | 256.59 seconds |
| Started | Sep 24 05:42:57 AM UTC 24 |
| Finished | Sep 24 05:47:17 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509590471 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1509590471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/97.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.950681779 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 343359605103 ps |
| CPU time | 423.99 seconds |
| Started | Sep 24 05:43:00 AM UTC 24 |
| Finished | Sep 24 05:50:09 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950681779 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.950681779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/98.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.4013278461 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 35211231296 ps |
| CPU time | 125.67 seconds |
| Started | Sep 24 05:43:04 AM UTC 24 |
| Finished | Sep 24 05:45:12 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013278461 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.4013278461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/rv_timer-sim-vcs/99.rv_timer_random/latest |
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