Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
138881111 |
1 |
|
|
T1 |
9195 |
|
T3 |
2708 |
|
T4 |
23689 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
68905972 |
1 |
|
|
T1 |
20 |
|
T3 |
255 |
|
T4 |
20439 |
auto[1] |
69975139 |
1 |
|
|
T1 |
9175 |
|
T3 |
2453 |
|
T4 |
3250 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
138875177 |
1 |
|
|
T1 |
9193 |
|
T3 |
2708 |
|
T4 |
23683 |
auto[1] |
5934 |
1 |
|
|
T1 |
2 |
|
T4 |
6 |
|
T6 |
5 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
68902998 |
1 |
|
|
T1 |
20 |
|
T3 |
255 |
|
T4 |
20435 |
all_values[0] |
auto[0] |
auto[1] |
2974 |
1 |
|
|
T4 |
4 |
|
T6 |
3 |
|
T7 |
2 |
all_values[0] |
auto[1] |
auto[0] |
69972179 |
1 |
|
|
T1 |
9173 |
|
T3 |
2453 |
|
T4 |
3248 |
all_values[0] |
auto[1] |
auto[1] |
2960 |
1 |
|
|
T1 |
2 |
|
T4 |
2 |
|
T6 |
2 |